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@@ -141,6 +141,8 @@
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#define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
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#define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
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+#define AD7192_EXT_FREQ_MHZ_MIN 2457600
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+#define AD7192_EXT_FREQ_MHZ_MAX 5120000
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#define AD7192_INT_FREQ_MHZ 4915200
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/* NOTE:
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@@ -218,6 +220,12 @@ static int ad7192_calibrate_all(struct ad7192_state *st)
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ARRAY_SIZE(ad7192_calib_arr));
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}
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+static inline bool ad7192_valid_external_frequency(u32 freq)
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+{
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+ return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
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+ freq <= AD7192_EXT_FREQ_MHZ_MAX);
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+}
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+
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static int ad7192_setup(struct ad7192_state *st,
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const struct ad7192_platform_data *pdata)
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{
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@@ -243,17 +251,20 @@ static int ad7192_setup(struct ad7192_state *st,
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id);
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switch (pdata->clock_source_sel) {
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- case AD7192_CLK_EXT_MCLK1_2:
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- case AD7192_CLK_EXT_MCLK2:
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- st->mclk = AD7192_INT_FREQ_MHZ;
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- break;
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case AD7192_CLK_INT:
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case AD7192_CLK_INT_CO:
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- if (pdata->ext_clk_hz)
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- st->mclk = pdata->ext_clk_hz;
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- else
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- st->mclk = AD7192_INT_FREQ_MHZ;
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+ st->mclk = AD7192_INT_FREQ_MHZ;
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break;
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+ case AD7192_CLK_EXT_MCLK1_2:
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+ case AD7192_CLK_EXT_MCLK2:
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+ if (ad7192_valid_external_frequency(pdata->ext_clk_hz)) {
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+ st->mclk = pdata->ext_clk_hz;
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+ break;
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+ }
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+ dev_err(&st->sd.spi->dev, "Invalid frequency setting %u\n",
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+ pdata->ext_clk_hz);
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+ ret = -EINVAL;
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+ goto out;
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default:
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ret = -EINVAL;
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goto out;
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