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@@ -240,6 +240,8 @@ static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
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return RREG32_DIDT(index);
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case CGS_IND_REG_GC_CAC:
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return RREG32_GC_CAC(index);
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+ case CGS_IND_REG_SE_CAC:
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+ return RREG32_SE_CAC(index);
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case CGS_IND_REG__AUDIO_ENDPT:
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DRM_ERROR("audio endpt register access not implemented.\n");
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return 0;
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@@ -266,6 +268,8 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
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return WREG32_DIDT(index, value);
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case CGS_IND_REG_GC_CAC:
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return WREG32_GC_CAC(index, value);
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+ case CGS_IND_REG_SE_CAC:
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+ return WREG32_SE_CAC(index, value);
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case CGS_IND_REG__AUDIO_ENDPT:
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DRM_ERROR("audio endpt register access not implemented.\n");
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return;
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