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@@ -100,16 +100,6 @@
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*/
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#define TX_QCHECK_PERIOD (HZ / 2)
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-/* SGE Hung Ingress DMA Threshold Warning time (in Hz) and Warning Repeat Rate
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- * (in RX_QCHECK_PERIOD multiples). If we find one of the SGE Ingress DMA
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- * State Machines in the same state for this amount of time (in HZ) then we'll
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- * issue a warning about a potential hang. We'll repeat the warning as the
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- * SGE Ingress DMA Channel appears to be hung every N RX_QCHECK_PERIODs till
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- * the situation clears. If the situation clears, we'll note that as well.
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- */
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-#define SGE_IDMA_WARN_THRESH (1 * HZ)
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-#define SGE_IDMA_WARN_REPEAT (20 * RX_QCHECK_PERIOD)
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-
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/*
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* Max number of Tx descriptors to be reclaimed by the Tx timer.
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*/
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@@ -1130,7 +1120,6 @@ cxgb_fcoe_offload(struct sk_buff *skb, struct adapter *adap,
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*/
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netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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- int len;
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u32 wr_mid;
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u64 cntrl, *end;
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int qidx, credits;
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@@ -1143,6 +1132,7 @@ netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev)
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const struct skb_shared_info *ssi;
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dma_addr_t addr[MAX_SKB_FRAGS + 1];
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bool immediate = false;
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+ int len, max_pkt_len;
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#ifdef CONFIG_CHELSIO_T4_FCOE
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int err;
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#endif /* CONFIG_CHELSIO_T4_FCOE */
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@@ -1156,6 +1146,13 @@ out_free: dev_kfree_skb_any(skb);
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return NETDEV_TX_OK;
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}
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+ /* Discard the packet if the length is greater than mtu */
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+ max_pkt_len = ETH_HLEN + dev->mtu;
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+ if (skb_vlan_tag_present(skb))
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+ max_pkt_len += VLAN_HLEN;
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+ if (!skb_shinfo(skb)->gso_size && (unlikely(skb->len > max_pkt_len)))
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+ goto out_free;
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+
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pi = netdev_priv(dev);
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adap = pi->adapter;
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qidx = skb_get_queue_mapping(skb);
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@@ -2279,7 +2276,7 @@ irq_handler_t t4_intr_handler(struct adapter *adap)
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static void sge_rx_timer_cb(unsigned long data)
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{
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unsigned long m;
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- unsigned int i, idma_same_state_cnt[2];
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+ unsigned int i;
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struct adapter *adap = (struct adapter *)data;
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struct sge *s = &adap->sge;
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@@ -2300,67 +2297,16 @@ static void sge_rx_timer_cb(unsigned long data)
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set_bit(id, s->starving_fl);
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}
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}
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+ /* The remainder of the SGE RX Timer Callback routine is dedicated to
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+ * global Master PF activities like checking for chip ingress stalls,
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+ * etc.
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+ */
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+ if (!(adap->flags & MASTER_PF))
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+ goto done;
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- t4_write_reg(adap, SGE_DEBUG_INDEX_A, 13);
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- idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH_A);
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- idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
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-
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- for (i = 0; i < 2; i++) {
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- u32 debug0, debug11;
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-
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- /* If the Ingress DMA Same State Counter ("timer") is less
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- * than 1s, then we can reset our synthesized Stall Timer and
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- * continue. If we have previously emitted warnings about a
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- * potential stalled Ingress Queue, issue a note indicating
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- * that the Ingress Queue has resumed forward progress.
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- */
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- if (idma_same_state_cnt[i] < s->idma_1s_thresh) {
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- if (s->idma_stalled[i] >= SGE_IDMA_WARN_THRESH)
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- CH_WARN(adap, "SGE idma%d, queue%u,resumed after %d sec\n",
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- i, s->idma_qid[i],
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- s->idma_stalled[i]/HZ);
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- s->idma_stalled[i] = 0;
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- continue;
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- }
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-
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- /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
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- * domain. The first time we get here it'll be because we
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- * passed the 1s Threshold; each additional time it'll be
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- * because the RX Timer Callback is being fired on its regular
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- * schedule.
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- *
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- * If the stall is below our Potential Hung Ingress Queue
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- * Warning Threshold, continue.
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- */
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- if (s->idma_stalled[i] == 0)
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- s->idma_stalled[i] = HZ;
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- else
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- s->idma_stalled[i] += RX_QCHECK_PERIOD;
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-
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- if (s->idma_stalled[i] < SGE_IDMA_WARN_THRESH)
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- continue;
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-
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- /* We'll issue a warning every SGE_IDMA_WARN_REPEAT Hz */
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- if (((s->idma_stalled[i] - HZ) % SGE_IDMA_WARN_REPEAT) != 0)
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- continue;
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-
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- /* Read and save the SGE IDMA State and Queue ID information.
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- * We do this every time in case it changes across time ...
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- */
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- t4_write_reg(adap, SGE_DEBUG_INDEX_A, 0);
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- debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
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- s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
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-
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- t4_write_reg(adap, SGE_DEBUG_INDEX_A, 11);
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- debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
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- s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
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-
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- CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n",
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- i, s->idma_qid[i], s->idma_state[i],
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- s->idma_stalled[i]/HZ, debug0, debug11);
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- t4_sge_decode_idma_state(adap, s->idma_state[i]);
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- }
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+ t4_idma_monitor(adap, &s->idma_monitor, HZ, RX_QCHECK_PERIOD);
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+done:
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mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
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}
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@@ -2437,9 +2383,12 @@ static void __iomem *bar2_address(struct adapter *adapter,
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return adapter->bar2 + bar2_qoffset;
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}
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+/* @intr_idx: MSI/MSI-X vector if >=0, -(absolute qid + 1) if < 0
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+ * @cong: < 0 -> no congestion feedback, >= 0 -> congestion channel map
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+ */
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int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
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struct net_device *dev, int intr_idx,
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- struct sge_fl *fl, rspq_handler_t hnd)
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+ struct sge_fl *fl, rspq_handler_t hnd, int cong)
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{
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int ret, flsz = 0;
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struct fw_iq_cmd c;
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@@ -2471,8 +2420,19 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
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FW_IQ_CMD_IQESIZE_V(ilog2(iq->iqe_len) - 4));
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c.iqsize = htons(iq->size);
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c.iqaddr = cpu_to_be64(iq->phys_addr);
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+ if (cong >= 0)
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+ c.iqns_to_fl0congen = htonl(FW_IQ_CMD_IQFLINTCONGEN_F);
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if (fl) {
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+ /* Allocate the ring for the hardware free list (with space
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+ * for its status page) along with the associated software
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+ * descriptor ring. The free list size needs to be a multiple
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+ * of the Egress Queue Unit and at least 2 Egress Units larger
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+ * than the SGE's Egress Congrestion Threshold
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+ * (fl_starve_thres - 1).
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+ */
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+ if (fl->size < s->fl_starve_thres - 1 + 2 * 8)
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+ fl->size = s->fl_starve_thres - 1 + 2 * 8;
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fl->size = roundup(fl->size, 8);
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fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64),
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sizeof(struct rx_sw_desc), &fl->addr,
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@@ -2481,10 +2441,15 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
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goto fl_nomem;
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flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
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- c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN_F |
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- FW_IQ_CMD_FL0FETCHRO_F |
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- FW_IQ_CMD_FL0DATARO_F |
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- FW_IQ_CMD_FL0PADEN_F);
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+ c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F |
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+ FW_IQ_CMD_FL0FETCHRO_F |
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+ FW_IQ_CMD_FL0DATARO_F |
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+ FW_IQ_CMD_FL0PADEN_F);
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+ if (cong >= 0)
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+ c.iqns_to_fl0congen |=
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+ htonl(FW_IQ_CMD_FL0CNGCHMAP_V(cong) |
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+ FW_IQ_CMD_FL0CONGCIF_F |
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+ FW_IQ_CMD_FL0CONGEN_F);
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c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN_V(2) |
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FW_IQ_CMD_FL0FBMAX_V(3));
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c.fl0size = htons(flsz);
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@@ -2532,6 +2497,41 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
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&fl->bar2_qid);
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refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL);
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}
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+
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+ /* For T5 and later we attempt to set up the Congestion Manager values
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+ * of the new RX Ethernet Queue. This should really be handled by
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+ * firmware because it's more complex than any host driver wants to
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+ * get involved with and it's different per chip and this is almost
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+ * certainly wrong. Firmware would be wrong as well, but it would be
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+ * a lot easier to fix in one place ... For now we do something very
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+ * simple (and hopefully less wrong).
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+ */
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+ if (!is_t4(adap->params.chip) && cong >= 0) {
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+ u32 param, val;
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+ int i;
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+
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+ param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
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+ FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
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+ FW_PARAMS_PARAM_YZ_V(iq->cntxt_id));
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+ if (cong == 0) {
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+ val = CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_QUEUE_X);
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+ } else {
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+ val =
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+ CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_CHANNEL_X);
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+ for (i = 0; i < 4; i++) {
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+ if (cong & (1 << i))
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+ val |=
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+ CONMCTXT_CNGCHMAP_V(1 << (i << 2));
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+ }
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+ }
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+ ret = t4_set_params(adap, adap->mbox, adap->fn, 0, 1,
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+ ¶m, &val);
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+ if (ret)
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+ dev_warn(adap->pdev_dev, "Failed to set Congestion"
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+ " Manager Context for Ingress Queue %d: %d\n",
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+ iq->cntxt_id, -ret);
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+ }
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+
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return 0;
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fl_nomem:
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@@ -2637,7 +2637,7 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
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txq->q.desc = alloc_ring(adap->pdev_dev, nentries,
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sizeof(struct tx_desc), 0, &txq->q.phys_addr,
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- NULL, 0, NUMA_NO_NODE);
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+ NULL, 0, dev_to_node(adap->pdev_dev));
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if (!txq->q.desc)
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return -ENOMEM;
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@@ -3067,11 +3067,11 @@ int t4_sge_init(struct adapter *adap)
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egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl);
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s->fl_starve_thres = 2*egress_threshold + 1;
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+ t4_idma_monitor_init(adap, &s->idma_monitor);
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+
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setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap);
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setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adap);
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- s->idma_1s_thresh = core_ticks_per_usec(adap) * 1000000; /* 1 s */
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- s->idma_stalled[0] = 0;
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- s->idma_stalled[1] = 0;
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+
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spin_lock_init(&s->intrq_lock);
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return 0;
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David S. Miller