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@@ -1869,6 +1869,12 @@ int i40e_vc_process_vflr_event(struct i40e_pf *pf)
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if (!test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
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return 0;
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+ /* re-enable vflr interrupt cause */
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+ reg = rd32(hw, I40E_PFINT_ICR0_ENA);
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+ reg |= I40E_PFINT_ICR0_ENA_VFLR_MASK;
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+ wr32(hw, I40E_PFINT_ICR0_ENA, reg);
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+ i40e_flush(hw);
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+
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clear_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
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for (vf_id = 0; vf_id < pf->num_alloc_vfs; vf_id++) {
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reg_idx = (hw->func_caps.vf_base_id + vf_id) / 32;
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@@ -1885,12 +1891,6 @@ int i40e_vc_process_vflr_event(struct i40e_pf *pf)
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}
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}
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- /* re-enable vflr interrupt cause */
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- reg = rd32(hw, I40E_PFINT_ICR0_ENA);
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- reg |= I40E_PFINT_ICR0_ENA_VFLR_MASK;
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- wr32(hw, I40E_PFINT_ICR0_ENA, reg);
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- i40e_flush(hw);
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-
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return 0;
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}
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