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@@ -286,6 +286,7 @@ MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
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enum mlxsw_reg_sfd_rec_type {
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MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
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+ MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
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};
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/* reg_sfd_rec_type
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@@ -376,24 +377,34 @@ MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
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MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
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MLXSW_REG_SFD_REC_LEN, 0x0C, false);
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-static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
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- enum mlxsw_reg_sfd_rec_policy policy,
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- const char *mac, u16 vid,
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- enum mlxsw_reg_sfd_rec_action action,
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- u8 local_port)
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+static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
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+ enum mlxsw_reg_sfd_rec_type rec_type,
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+ enum mlxsw_reg_sfd_rec_policy policy,
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+ const char *mac,
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+ enum mlxsw_reg_sfd_rec_action action)
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{
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u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
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if (rec_index >= num_rec)
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mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
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mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
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- mlxsw_reg_sfd_rec_type_set(payload, rec_index,
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- MLXSW_REG_SFD_REC_TYPE_UNICAST);
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+ mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
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mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
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mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
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+ mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
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+}
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+
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+static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
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+ enum mlxsw_reg_sfd_rec_policy policy,
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+ const char *mac, u16 vid,
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+ enum mlxsw_reg_sfd_rec_action action,
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+ u8 local_port)
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+{
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+ mlxsw_reg_sfd_rec_pack(payload, rec_index,
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+ MLXSW_REG_SFD_REC_TYPE_UNICAST,
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+ policy, mac, action);
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mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
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mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, vid);
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- mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
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mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
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}
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@@ -406,6 +417,58 @@ static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
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*p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
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}
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+/* reg_sfd_uc_lag_sub_port
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+ * LAG sub port.
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+ * Must be 0 if multichannel VEPA is not enabled.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
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+ MLXSW_REG_SFD_REC_LEN, 0x08, false);
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+
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+/* reg_sfd_uc_lag_fid_vid
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+ * Filtering ID or VLAN ID
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+ * For SwitchX and SwitchX-2:
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+ * - Dynamic entries (policy 2,3) use FID
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+ * - Static entries (policy 0) use VID
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+ * - When independent learning is configured, VID=FID
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+ * For Spectrum: use FID for both Dynamic and Static entries.
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+ * VID should not be used.
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+ * Access: Index
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+ */
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+MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
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+ MLXSW_REG_SFD_REC_LEN, 0x08, false);
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+
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+/* reg_sfd_uc_lag_lag_id
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+ * LAG Identifier - pointer into the LAG descriptor table.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
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+ MLXSW_REG_SFD_REC_LEN, 0x0C, false);
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+
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+static inline void
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+mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
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+ enum mlxsw_reg_sfd_rec_policy policy,
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+ const char *mac, u16 vid,
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+ enum mlxsw_reg_sfd_rec_action action,
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+ u16 lag_id)
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+{
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+ mlxsw_reg_sfd_rec_pack(payload, rec_index,
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+ MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
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+ policy, mac, action);
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+ mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
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+ mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, vid);
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+ mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
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+}
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+
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+static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
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+ char *mac, u16 *p_vid,
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+ u16 *p_lag_id)
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+{
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+ mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
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+ *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
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+ *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
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+}
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+
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/* SFN - Switch FDB Notification Register
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* -------------------------------------------
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* The switch provides notifications on newly learned FDB entries and
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@@ -456,8 +519,12 @@ MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
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enum mlxsw_reg_sfn_rec_type {
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/* MAC addresses learned on a regular port. */
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MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
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- /* Aged-out MAC address on a regular port */
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+ /* MAC addresses learned on a LAG port. */
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+ MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
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+ /* Aged-out MAC address on a regular port. */
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MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
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+ /* Aged-out MAC address on a LAG port. */
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+ MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
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};
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/* reg_sfn_rec_type
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@@ -505,6 +572,22 @@ static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
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*p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
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}
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+/* reg_sfn_mac_lag_lag_id
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+ * LAG ID (pointer into the LAG descriptor table).
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+ * Access: RO
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+ */
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+MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
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+ MLXSW_REG_SFN_REC_LEN, 0x0C, false);
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+
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+static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
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+ char *mac, u16 *p_vid,
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+ u16 *p_lag_id)
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+{
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+ mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
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+ *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
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+ *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
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+}
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+
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/* SPMS - Switch Port MSTP/RSTP State Register
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* -------------------------------------------
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* Configures the spanning tree state of a physical port.
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@@ -865,6 +948,293 @@ static inline void mlxsw_reg_sftr_pack(char *payload,
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mlxsw_reg_sftr_port_mask_set(payload, port, 1);
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}
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+/* SLDR - Switch LAG Descriptor Register
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+ * -----------------------------------------
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+ * The switch LAG descriptor register is populated by LAG descriptors.
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+ * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
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+ * max_lag-1.
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+ */
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+#define MLXSW_REG_SLDR_ID 0x2014
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+#define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
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+
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+static const struct mlxsw_reg_info mlxsw_reg_sldr = {
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+ .id = MLXSW_REG_SLDR_ID,
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+ .len = MLXSW_REG_SLDR_LEN,
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+};
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+
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+enum mlxsw_reg_sldr_op {
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+ /* Indicates a creation of a new LAG-ID, lag_id must be valid */
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+ MLXSW_REG_SLDR_OP_LAG_CREATE,
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+ MLXSW_REG_SLDR_OP_LAG_DESTROY,
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+ /* Ports that appear in the list have the Distributor enabled */
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+ MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
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+ /* Removes ports from the disributor list */
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+ MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
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+};
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+
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+/* reg_sldr_op
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+ * Operation.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
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+
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+/* reg_sldr_lag_id
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+ * LAG identifier. The lag_id is the index into the LAG descriptor table.
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+ * Access: Index
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+ */
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+MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
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+
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+static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
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+{
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+ MLXSW_REG_ZERO(sldr, payload);
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+ mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
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+ mlxsw_reg_sldr_lag_id_set(payload, lag_id);
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+}
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+
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+static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
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+{
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+ MLXSW_REG_ZERO(sldr, payload);
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+ mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
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+ mlxsw_reg_sldr_lag_id_set(payload, lag_id);
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+}
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+
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+/* reg_sldr_num_ports
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+ * The number of member ports of the LAG.
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+ * Reserved for Create / Destroy operations
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+ * For Add / Remove operations - indicates the number of ports in the list.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
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+
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+/* reg_sldr_system_port
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+ * System port.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
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+
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+static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
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+ u8 local_port)
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+{
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+ MLXSW_REG_ZERO(sldr, payload);
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+ mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
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+ mlxsw_reg_sldr_lag_id_set(payload, lag_id);
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+ mlxsw_reg_sldr_num_ports_set(payload, 1);
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+ mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
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+}
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+
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+static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
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+ u8 local_port)
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+{
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+ MLXSW_REG_ZERO(sldr, payload);
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+ mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
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+ mlxsw_reg_sldr_lag_id_set(payload, lag_id);
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+ mlxsw_reg_sldr_num_ports_set(payload, 1);
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+ mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
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+}
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+
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+/* SLCR - Switch LAG Configuration 2 Register
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+ * -------------------------------------------
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+ * The Switch LAG Configuration register is used for configuring the
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+ * LAG properties of the switch.
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+ */
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+#define MLXSW_REG_SLCR_ID 0x2015
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+#define MLXSW_REG_SLCR_LEN 0x10
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+
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+static const struct mlxsw_reg_info mlxsw_reg_slcr = {
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+ .id = MLXSW_REG_SLCR_ID,
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+ .len = MLXSW_REG_SLCR_LEN,
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+};
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+
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+enum mlxsw_reg_slcr_pp {
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+ /* Global Configuration (for all ports) */
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+ MLXSW_REG_SLCR_PP_GLOBAL,
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+ /* Per port configuration, based on local_port field */
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+ MLXSW_REG_SLCR_PP_PER_PORT,
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+};
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+
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+/* reg_slcr_pp
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+ * Per Port Configuration
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+ * Note: Reading at Global mode results in reading port 1 configuration.
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+ * Access: Index
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+ */
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+MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
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+
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+/* reg_slcr_local_port
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+ * Local port number
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+ * Supported from CPU port
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+ * Not supported from router port
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+ * Reserved when pp = Global Configuration
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+ * Access: Index
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+ */
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+MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
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+
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+enum mlxsw_reg_slcr_type {
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+ MLXSW_REG_SLCR_TYPE_CRC, /* default */
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+ MLXSW_REG_SLCR_TYPE_XOR,
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+ MLXSW_REG_SLCR_TYPE_RANDOM,
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+};
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+
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+/* reg_slcr_type
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+ * Hash type
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
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+
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+/* Ingress port */
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+#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
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+/* SMAC - for IPv4 and IPv6 packets */
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+#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
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+/* SMAC - for non-IP packets */
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+#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
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+#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
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+ (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
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+ MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
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+/* DMAC - for IPv4 and IPv6 packets */
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+#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
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+/* DMAC - for non-IP packets */
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+#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
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+#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
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+ (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
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+ MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
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+/* Ethertype - for IPv4 and IPv6 packets */
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+#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
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+/* Ethertype - for non-IP packets */
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+#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
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+#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
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+ (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
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+ MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
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+/* VLAN ID - for IPv4 and IPv6 packets */
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+#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
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+/* VLAN ID - for non-IP packets */
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+#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
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+#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
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+ (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
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+ MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
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+/* Source IP address (can be IPv4 or IPv6) */
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+#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
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+/* Destination IP address (can be IPv4 or IPv6) */
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+#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
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+/* TCP/UDP source port */
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+#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
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+/* TCP/UDP destination port*/
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+#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
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+/* IPv4 Protocol/IPv6 Next Header */
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+#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
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+/* IPv6 Flow label */
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+#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
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+/* SID - FCoE source ID */
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|
|
+#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
|
|
|
+/* DID - FCoE destination ID */
|
|
|
+#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
|
|
|
+/* OXID - FCoE originator exchange ID */
|
|
|
+#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
|
|
|
+/* Destination QP number - for RoCE packets */
|
|
|
+#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
|
|
|
+
|
|
|
+/* reg_slcr_lag_hash
|
|
|
+ * LAG hashing configuration. This is a bitmask, in which each set
|
|
|
+ * bit includes the corresponding item in the LAG hash calculation.
|
|
|
+ * The default lag_hash contains SMAC, DMAC, VLANID and
|
|
|
+ * Ethertype (for all packet types).
|
|
|
+ * Access: RW
|
|
|
+ */
|
|
|
+MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
|
|
|
+
|
|
|
+static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
|
|
|
+{
|
|
|
+ MLXSW_REG_ZERO(slcr, payload);
|
|
|
+ mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
|
|
|
+ mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR);
|
|
|
+ mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
|
|
|
+}
|
|
|
+
|
|
|
+/* SLCOR - Switch LAG Collector Register
|
|
|
+ * -------------------------------------
|
|
|
+ * The Switch LAG Collector register controls the Local Port membership
|
|
|
+ * in a LAG and enablement of the collector.
|
|
|
+ */
|
|
|
+#define MLXSW_REG_SLCOR_ID 0x2016
|
|
|
+#define MLXSW_REG_SLCOR_LEN 0x10
|
|
|
+
|
|
|
+static const struct mlxsw_reg_info mlxsw_reg_slcor = {
|
|
|
+ .id = MLXSW_REG_SLCOR_ID,
|
|
|
+ .len = MLXSW_REG_SLCOR_LEN,
|
|
|
+};
|
|
|
+
|
|
|
+enum mlxsw_reg_slcor_col {
|
|
|
+ /* Port is added with collector disabled */
|
|
|
+ MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
|
|
|
+ MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
|
|
|
+ MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
|
|
|
+ MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
|
|
|
+};
|
|
|
+
|
|
|
+/* reg_slcor_col
|
|
|
+ * Collector configuration
|
|
|
+ * Access: RW
|
|
|
+ */
|
|
|
+MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
|
|
|
+
|
|
|
+/* reg_slcor_local_port
|
|
|
+ * Local port number
|
|
|
+ * Not supported for CPU port
|
|
|
+ * Access: Index
|
|
|
+ */
|
|
|
+MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
|
|
|
+
|
|
|
+/* reg_slcor_lag_id
|
|
|
+ * LAG Identifier. Index into the LAG descriptor table.
|
|
|
+ * Access: Index
|
|
|
+ */
|
|
|
+MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
|
|
|
+
|
|
|
+/* reg_slcor_port_index
|
|
|
+ * Port index in the LAG list. Only valid on Add Port to LAG col.
|
|
|
+ * Valid range is from 0 to cap_max_lag_members-1
|
|
|
+ * Access: RW
|
|
|
+ */
|
|
|
+MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
|
|
|
+
|
|
|
+static inline void mlxsw_reg_slcor_pack(char *payload,
|
|
|
+ u8 local_port, u16 lag_id,
|
|
|
+ enum mlxsw_reg_slcor_col col)
|
|
|
+{
|
|
|
+ MLXSW_REG_ZERO(slcor, payload);
|
|
|
+ mlxsw_reg_slcor_col_set(payload, col);
|
|
|
+ mlxsw_reg_slcor_local_port_set(payload, local_port);
|
|
|
+ mlxsw_reg_slcor_lag_id_set(payload, lag_id);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
|
|
|
+ u8 local_port, u16 lag_id,
|
|
|
+ u8 port_index)
|
|
|
+{
|
|
|
+ mlxsw_reg_slcor_pack(payload, local_port, lag_id,
|
|
|
+ MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
|
|
|
+ mlxsw_reg_slcor_port_index_set(payload, port_index);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
|
|
|
+ u8 local_port, u16 lag_id)
|
|
|
+{
|
|
|
+ mlxsw_reg_slcor_pack(payload, local_port, lag_id,
|
|
|
+ MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
|
|
|
+ u8 local_port, u16 lag_id)
|
|
|
+{
|
|
|
+ mlxsw_reg_slcor_pack(payload, local_port, lag_id,
|
|
|
+ MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
|
|
|
+ u8 local_port, u16 lag_id)
|
|
|
+{
|
|
|
+ mlxsw_reg_slcor_pack(payload, local_port, lag_id,
|
|
|
+ MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
|
|
|
+}
|
|
|
+
|
|
|
/* SPMLR - Switch Port MAC Learning Register
|
|
|
* -----------------------------------------
|
|
|
* Controls the Switch MAC learning policy per port.
|
|
@@ -2653,6 +3023,12 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id)
|
|
|
return "SFGC";
|
|
|
case MLXSW_REG_SFTR_ID:
|
|
|
return "SFTR";
|
|
|
+ case MLXSW_REG_SLDR_ID:
|
|
|
+ return "SLDR";
|
|
|
+ case MLXSW_REG_SLCR_ID:
|
|
|
+ return "SLCR";
|
|
|
+ case MLXSW_REG_SLCOR_ID:
|
|
|
+ return "SLCOR";
|
|
|
case MLXSW_REG_SPMLR_ID:
|
|
|
return "SPMLR";
|
|
|
case MLXSW_REG_SVFA_ID:
|