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drm/amd/display: fix segfault on insufficient TG during validation

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin 7 years ago
parent
fc6de1c565
commit
c5b38aec26
1 changed files with 1 additions and 1 deletions
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  1. 1 1
      drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+ 1 - 1
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File 

@@ -1700,7 +1700,7 @@ enum dc_status resource_map_pool_resources(
 
 		pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
 
 		pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
 
 #endif
 
 #endif
 
 
 
-	if (pipe_idx < 0)
 
+	if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
 
 		return DC_NO_CONTROLLER_RESOURCE;
 
 		return DC_NO_CONTROLLER_RESOURCE;
 
 
 
 	pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
 
 	pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];