drm/sti: vtg fix CEA-861E video format timing error

HDMI analyzer tests showed that Vsync and Hsync signal were not
compliant with the HDMI protocol.

HDMI_DELAY should be taken into account in the VTG Vsync
programming to reflect the 6 pixels shift introduced in the VTG
Hsync programming.

Signed-off-by: Vincent Abriou <vincent.abriou@st.com>

drivers/gpu/drm/sti/sti_vtg.c

@@ -173,8 +173,11 @@ static void vtg_set_mode(struct sti_vtg *vtg,
 	tmp |= 1;
 	writel(tmp, vtg->regs + VTG_TOP_V_VD_1);
 	writel(tmp, vtg->regs + VTG_BOT_V_VD_1);
-	writel(0, vtg->regs + VTG_TOP_V_HD_1);
-	writel(0, vtg->regs + VTG_BOT_V_HD_1);
+
+	tmp = HDMI_DELAY << 16;
+	tmp |= HDMI_DELAY;
+	writel(tmp, vtg->regs + VTG_TOP_V_HD_1);
+	writel(tmp, vtg->regs + VTG_BOT_V_HD_1);
 
 	/* prepare VTG set 2 for for HD DCS */
 	tmp = (mode->hsync_end - mode->hsync_start) << 16;