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dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate

Add two properties of ref_clk and coefficient used by U2 slew rate
calibrate which may vary on different SoCs

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Chunfeng Yun 7 years ago
parent
8833ebf4f8
commit
c55fbcb8cf
1 changed files with 4 additions and 0 deletions
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  1. 4 0
      Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt

+ 4 - 0
Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
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@@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
 
  - reg		: offset and length of register shared by multiple ports,
 
  - reg		: offset and length of register shared by multiple ports,
 
 		  exclude port's private register. It is needed on mt2701
 
 		  exclude port's private register. It is needed on mt2701
 
 		  and mt8173, but not on mt2712.
 
 		  and mt8173, but not on mt2712.
 
+ - mediatek,src-ref-clk-mhz	: frequency of reference clock for slew rate
 
+		  calibrate
 
+ - mediatek,src-coef	: coefficient for slew rate calibrate, depends on
 
+		  SoC process
 
 
 
 Required properties (port (child) node):
 
 Required properties (port (child) node):
 
 - reg		: address and length of the register set for the port.
 
 - reg		: address and length of the register set for the port.