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@@ -392,7 +392,16 @@ static int gmc_v9_0_early_init(void *handle)
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static int gmc_v9_0_late_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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- unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 3, 3 };
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+ /*
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+ * The latest engine allocation on gfx9 is:
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+ * Engine 0, 1: idle
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+ * Engine 2, 3: firmware
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+ * Engine 4~13: amdgpu ring, subject to change when ring number changes
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+ * Engine 14~15: idle
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+ * Engine 16: kfd tlb invalidation
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+ * Engine 17: Gart flushes
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+ */
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+ unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
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unsigned i;
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for(i = 0; i < adev->num_rings; ++i) {
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@@ -405,9 +414,9 @@ static int gmc_v9_0_late_init(void *handle)
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ring->funcs->vmhub);
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}
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- /* Engine 17 is used for GART flushes */
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+ /* Engine 16 is used for KFD and 17 for GART flushes */
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for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
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- BUG_ON(vm_inv_eng[i] > 17);
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+ BUG_ON(vm_inv_eng[i] > 16);
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return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
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}
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