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@@ -665,6 +665,16 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
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unsigned i;
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u32 base, limit, high;
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struct resource *res, *conflict;
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+ struct pci_dev *other;
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+
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+ /* Check that we are the only device of that type */
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+ other = pci_get_device(dev->vendor, dev->device, NULL);
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+ if (other != dev ||
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+ (other = pci_get_device(dev->vendor, dev->device, other))) {
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+ /* This is a multi-socket system, don't touch it for now */
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+ pci_dev_put(other);
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+ return;
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+ }
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for (i = 0; i < 8; i++) {
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pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base);
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@@ -696,8 +706,13 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
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res->end = 0xfd00000000ull - 1;
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/* Just grab the free area behind system memory for this */
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- while ((conflict = request_resource_conflict(&iomem_resource, res)))
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+ while ((conflict = request_resource_conflict(&iomem_resource, res))) {
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+ if (conflict->end >= res->end) {
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+ kfree(res);
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+ return;
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+ }
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res->start = conflict->end + 1;
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+ }
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dev_info(&dev->dev, "adding root bus resource %pR\n", res);
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@@ -714,10 +729,10 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
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pci_bus_add_resource(dev->bus, res, 0);
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}
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-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
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-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
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-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
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-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
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-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
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#endif
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