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@@ -4078,6 +4078,22 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
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}
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}
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+/* Return which DP Port should be selected for Transcoder DP control */
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+static enum port
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+intel_trans_dp_port_sel(struct drm_crtc *crtc)
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+{
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+ struct drm_device *dev = crtc->dev;
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+ struct intel_encoder *encoder;
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+
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+ for_each_encoder_on_crtc(dev, crtc, encoder) {
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+ if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
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+ encoder->type == INTEL_OUTPUT_EDP)
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+ return enc_to_dig_port(&encoder->base)->port;
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+ }
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+
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+ return -1;
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+}
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+
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/*
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* Enable PCH resources required for PCH ports:
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* - PCH PLLs
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@@ -4156,13 +4172,13 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
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temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
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switch (intel_trans_dp_port_sel(crtc)) {
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- case PCH_DP_B:
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+ case PORT_B:
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temp |= TRANS_DP_PORT_SEL_B;
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break;
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- case PCH_DP_C:
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+ case PORT_C:
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temp |= TRANS_DP_PORT_SEL_C;
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break;
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- case PCH_DP_D:
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+ case PORT_D:
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temp |= TRANS_DP_PORT_SEL_D;
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break;
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default:
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