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@@ -37,6 +37,7 @@
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#define SSDR (0x10) /* SSP Data Write/Data Read Register */
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#define SSDR (0x10) /* SSP Data Write/Data Read Register */
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#define SSTO (0x28) /* SSP Time Out Register */
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#define SSTO (0x28) /* SSP Time Out Register */
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+#define DDS_RATE (0x28) /* SSP DDS Clock Rate Register (Intel Quark) */
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#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
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#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
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#define SSTSA (0x30) /* SSP Tx Timeslot Active */
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#define SSTSA (0x30) /* SSP Tx Timeslot Active */
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#define SSRSA (0x34) /* SSP Rx Timeslot Active */
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#define SSRSA (0x34) /* SSP Rx Timeslot Active */
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