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@@ -384,7 +384,7 @@
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#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
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#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
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#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
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-#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT);
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+#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
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#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
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#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
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#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
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