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@@ -370,7 +370,7 @@ static int collect_cpu_info_early(struct ucode_cpu_info *uci)
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native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
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csig.pf = 1 << ((val[1] >> 18) & 7);
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}
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- native_wrmsr(MSR_IA32_UCODE_REV, 0, 0);
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+ native_wrmsrl(MSR_IA32_UCODE_REV, 0);
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/* As documented in the SDM: Do a CPUID 1 here */
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sync_core();
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@@ -648,10 +648,8 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
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return 0;
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/* write microcode via MSR 0x79 */
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- native_wrmsr(MSR_IA32_UCODE_WRITE,
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- (unsigned long)mc->bits,
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- (unsigned long)mc->bits >> 16 >> 16);
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- native_wrmsr(MSR_IA32_UCODE_REV, 0, 0);
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+ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
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+ native_wrmsrl(MSR_IA32_UCODE_REV, 0);
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/* As documented in the SDM: Do a CPUID 1 here */
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sync_core();
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@@ -860,10 +858,8 @@ static int apply_microcode_intel(int cpu)
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return 0;
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/* write microcode via MSR 0x79 */
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- wrmsr(MSR_IA32_UCODE_WRITE,
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- (unsigned long) mc->bits,
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- (unsigned long) mc->bits >> 16 >> 16);
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- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
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+ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
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+ wrmsrl(MSR_IA32_UCODE_REV, 0);
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/* As documented in the SDM: Do a CPUID 1 here */
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sync_core();
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