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@@ -1640,8 +1640,8 @@ void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
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i -= rx_ring->count;
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}
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- /* clear the status bits for the next_to_use descriptor */
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- rx_desc->wb.upper.status_error = 0;
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+ /* clear the length for the next_to_use descriptor */
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+ rx_desc->wb.upper.length = 0;
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cleaned_count--;
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} while (cleaned_count);
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@@ -2154,7 +2154,7 @@ static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
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rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
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- if (!rx_desc->wb.upper.status_error)
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+ if (!rx_desc->wb.upper.length)
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break;
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/* This memory barrier is needed to keep us from reading
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@@ -3698,6 +3698,7 @@ void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
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struct ixgbe_ring *ring)
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{
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struct ixgbe_hw *hw = &adapter->hw;
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+ union ixgbe_adv_rx_desc *rx_desc;
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u64 rdba = ring->dma;
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u32 rxdctl;
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u8 reg_idx = ring->reg_idx;
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@@ -3732,6 +3733,10 @@ void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
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rxdctl |= 0x080420;
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}
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+ /* initialize Rx descriptor 0 */
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+ rx_desc = IXGBE_RX_DESC(ring, 0);
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+ rx_desc->wb.upper.length = 0;
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+
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/* enable receive descriptor ring */
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rxdctl |= IXGBE_RXDCTL_ENABLE;
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IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
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@@ -4940,9 +4945,6 @@ static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
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size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
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memset(rx_ring->rx_buffer_info, 0, size);
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- /* Zero out the descriptor ring */
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- memset(rx_ring->desc, 0, rx_ring->size);
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-
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rx_ring->next_to_alloc = 0;
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rx_ring->next_to_clean = 0;
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rx_ring->next_to_use = 0;
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