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@@ -6569,12 +6569,12 @@ static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
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switch (state) {
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case AMDGPU_IRQ_STATE_DISABLE:
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cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
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- cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
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+ cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
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WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
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break;
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case AMDGPU_IRQ_STATE_ENABLE:
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cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
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- cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
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+ cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
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WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
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break;
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default:
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@@ -6586,12 +6586,12 @@ static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
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switch (state) {
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case AMDGPU_IRQ_STATE_DISABLE:
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cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
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- cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
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+ cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
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WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
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break;
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case AMDGPU_IRQ_STATE_ENABLE:
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cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
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- cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
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+ cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
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WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
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break;
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default:
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