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@@ -127,53 +127,51 @@ static void dwmac4_dma_init(void __iomem *ioaddr,
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dwmac4_dma_init_channel(ioaddr, dma_cfg, dma_tx, dma_rx, i);
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}
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-static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel)
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+static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
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+ u32 *reg_space)
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{
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- pr_debug(" Channel %d\n", channel);
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- pr_debug("\tDMA_CHAN_CONTROL, offset: 0x%x, val: 0x%x\n", 0,
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- readl(ioaddr + DMA_CHAN_CONTROL(channel)));
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- pr_debug("\tDMA_CHAN_TX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x4,
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- readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)));
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- pr_debug("\tDMA_CHAN_RX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x8,
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- readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)));
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- pr_debug("\tDMA_CHAN_TX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x14,
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- readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)));
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- pr_debug("\tDMA_CHAN_RX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x1c,
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- readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)));
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- pr_debug("\tDMA_CHAN_TX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x20,
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- readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)));
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- pr_debug("\tDMA_CHAN_RX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x28,
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- readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)));
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- pr_debug("\tDMA_CHAN_TX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x2c,
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- readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)));
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- pr_debug("\tDMA_CHAN_RX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x30,
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- readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)));
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- pr_debug("\tDMA_CHAN_INTR_ENA, offset: 0x%x, val: 0x%x\n", 0x34,
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- readl(ioaddr + DMA_CHAN_INTR_ENA(channel)));
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- pr_debug("\tDMA_CHAN_RX_WATCHDOG, offset: 0x%x, val: 0x%x\n", 0x38,
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- readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)));
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- pr_debug("\tDMA_CHAN_SLOT_CTRL_STATUS, offset: 0x%x, val: 0x%x\n", 0x3c,
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- readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)));
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- pr_debug("\tDMA_CHAN_CUR_TX_DESC, offset: 0x%x, val: 0x%x\n", 0x44,
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- readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)));
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- pr_debug("\tDMA_CHAN_CUR_RX_DESC, offset: 0x%x, val: 0x%x\n", 0x4c,
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- readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)));
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- pr_debug("\tDMA_CHAN_CUR_TX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x54,
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- readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)));
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- pr_debug("\tDMA_CHAN_CUR_RX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x5c,
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- readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)));
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- pr_debug("\tDMA_CHAN_STATUS, offset: 0x%x, val: 0x%x\n", 0x60,
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- readl(ioaddr + DMA_CHAN_STATUS(channel)));
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+ reg_space[DMA_CHAN_CONTROL(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_CONTROL(channel));
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+ reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
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+ reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
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+ reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
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+ reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
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+ reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
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+ reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
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+ reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
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+ reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
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+ reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
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+ reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
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+ reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
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+ reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
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+ reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
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+ reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
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+ reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
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+ reg_space[DMA_CHAN_STATUS(channel) / 4] =
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+ readl(ioaddr + DMA_CHAN_STATUS(channel));
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}
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-static void dwmac4_dump_dma_regs(void __iomem *ioaddr)
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+static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
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{
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int i;
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- pr_debug(" GMAC4 DMA registers\n");
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-
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for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
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- _dwmac4_dump_dma_regs(ioaddr, i);
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+ _dwmac4_dump_dma_regs(ioaddr, i, reg_space);
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}
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static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt)
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