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@@ -3525,7 +3525,7 @@ static void gen6_enable_rps(struct drm_device *dev)
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gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
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}
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-void gen6_update_ring_freq(struct drm_device *dev)
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+static void __gen6_update_ring_freq(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int min_freq = 15;
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@@ -3595,6 +3595,18 @@ void gen6_update_ring_freq(struct drm_device *dev)
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}
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}
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+void gen6_update_ring_freq(struct drm_device *dev)
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+{
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+
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+ if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
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+ return;
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+
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+ mutex_lock(&dev_priv->rps.hw_lock);
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+ __gen6_update_ring_freq(dev);
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+ mutex_unlock(&dev_priv->rps.hw_lock);
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+}
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+
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int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
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{
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u32 val, rp0;
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@@ -4566,10 +4578,10 @@ static void intel_gen6_powersave_work(struct work_struct *work)
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valleyview_enable_rps(dev);
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} else if (IS_BROADWELL(dev)) {
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gen8_enable_rps(dev);
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- gen6_update_ring_freq(dev);
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+ __gen6_update_ring_freq(dev);
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} else {
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gen6_enable_rps(dev);
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- gen6_update_ring_freq(dev);
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+ __gen6_update_ring_freq(dev);
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}
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dev_priv->rps.enabled = true;
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mutex_unlock(&dev_priv->rps.hw_lock);
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