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@@ -584,6 +584,15 @@
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reg = <0x0 0x7000e400 0x0 0x400>;
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clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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+
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+ powergates {
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+ pd_audio: aud {
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+ clocks = <&tegra_car TEGRA210_CLK_APE>,
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+ <&tegra_car TEGRA210_CLK_APB2APE>;
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+ resets = <&tegra_car 198>;
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+ #power-domain-cells = <0>;
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+ };
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+ };
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};
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fuse@7000f800 {
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