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@@ -72,6 +72,8 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
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}
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ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);
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+ ctx->init_priority = priority;
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+ ctx->override_priority = AMD_SCHED_PRIORITY_UNSET;
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/* create context entity for each ring */
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for (i = 0; i < adev->num_rings; i++) {
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@@ -362,6 +364,33 @@ struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
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return fence;
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}
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+void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
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+ enum amd_sched_priority priority)
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+{
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+ int i;
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+ struct amdgpu_device *adev = ctx->adev;
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+ struct amd_sched_rq *rq;
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+ struct amd_sched_entity *entity;
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+ struct amdgpu_ring *ring;
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+ enum amd_sched_priority ctx_prio;
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+
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+ ctx->override_priority = priority;
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+
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+ ctx_prio = (ctx->override_priority == AMD_SCHED_PRIORITY_UNSET) ?
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+ ctx->init_priority : ctx->override_priority;
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+
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+ for (i = 0; i < adev->num_rings; i++) {
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+ ring = adev->rings[i];
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+ entity = &ctx->rings[i].entity;
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+ rq = &ring->sched.sched_rq[ctx_prio];
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+
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+ if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
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+ continue;
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+
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+ amd_sched_entity_set_rq(entity, rq);
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+ }
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+}
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+
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void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
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{
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mutex_init(&mgr->lock);
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