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@@ -26,7 +26,6 @@
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <asm/sysreg.h>
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#include <asm/sysreg.h>
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-static bool mixed_endian_el0 = true;
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unsigned long elf_hwcap __read_mostly;
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unsigned long elf_hwcap __read_mostly;
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EXPORT_SYMBOL_GPL(elf_hwcap);
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EXPORT_SYMBOL_GPL(elf_hwcap);
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@@ -44,22 +43,6 @@ unsigned int compat_elf_hwcap2 __read_mostly;
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DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
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DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
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-
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-bool cpu_supports_mixed_endian_el0(void)
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-{
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- return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
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-}
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-
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-bool system_supports_mixed_endian_el0(void)
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-{
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- return mixed_endian_el0;
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-}
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-
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-static void update_mixed_endian_el0_support(struct cpuinfo_arm64 *info)
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-{
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- mixed_endian_el0 &= id_aa64mmfr0_mixed_endian_el0(info->reg_id_aa64mmfr0);
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-}
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-
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#define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
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#define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
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{ \
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{ \
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.strict = STRICT, \
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.strict = STRICT, \
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@@ -433,9 +416,6 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
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init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
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init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
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init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
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init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
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init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
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init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
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-
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- /* This will be removed later, once we start using the infrastructure */
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- update_mixed_endian_el0_support(info);
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}
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}
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static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
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static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
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@@ -586,8 +566,6 @@ void update_cpu_features(int cpu,
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*/
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*/
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WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
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WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
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"Unsupported CPU feature variation.\n");
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"Unsupported CPU feature variation.\n");
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-
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- update_mixed_endian_el0_support(info);
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}
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}
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u64 read_system_reg(u32 id)
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u64 read_system_reg(u32 id)
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