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@@ -206,7 +206,7 @@ enum {
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#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
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#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
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#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
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-#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
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+/* Free LONG_ASM_CONST(0x0020000000000000) */
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#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
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#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
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#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
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@@ -451,7 +451,7 @@ enum {
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
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- CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
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+ CPU_FTR_CFAR | CPU_FTR_HVMODE | \
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CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
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#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
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@@ -460,7 +460,7 @@ enum {
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_DSCR | CPU_FTR_SAO | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
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- CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
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+ CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
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CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
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CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
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#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
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