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@@ -375,12 +375,10 @@ static void __init mx50_clocks_init(struct device_node *np)
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}
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CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
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-int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
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- unsigned long rate_ckih1, unsigned long rate_ckih2)
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+static void __init mx51_clocks_init(struct device_node *np)
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{
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int i;
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u32 val;
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- struct device_node *np;
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clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
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clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
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@@ -422,12 +420,11 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
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pr_err("i.MX51 clk %d: register failed with %ld\n",
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i, PTR_ERR(clk[i]));
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- np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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- mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
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+ mx5_clocks_common_init(0, 0, 0, 0);
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clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
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clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
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@@ -474,15 +471,8 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
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val = readl(MXC_CCM_CLPCR);
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val |= 1 << 23;
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writel(val, MXC_CCM_CLPCR);
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-
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- return 0;
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-}
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-
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-static void __init mx51_clocks_init_dt(struct device_node *np)
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-{
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- mx51_clocks_init(0, 0, 0, 0);
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}
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-CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
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+CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
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static void __init mx53_clocks_init(struct device_node *np)
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{
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