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@@ -822,7 +822,7 @@ static int i40e_get_eeprom(struct net_device *netdev,
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struct i40e_netdev_priv *np = netdev_priv(netdev);
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struct i40e_hw *hw = &np->vsi->back->hw;
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struct i40e_pf *pf = np->vsi->back;
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- int ret_val = 0, len;
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+ int ret_val = 0, len, offset;
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u8 *eeprom_buff;
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u16 i, sectors;
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bool last;
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@@ -835,19 +835,21 @@ static int i40e_get_eeprom(struct net_device *netdev,
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/* check for NVMUpdate access method */
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magic = hw->vendor_id | (hw->device_id << 16);
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if (eeprom->magic && eeprom->magic != magic) {
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+ struct i40e_nvm_access *cmd;
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int errno;
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/* make sure it is the right magic for NVMUpdate */
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if ((eeprom->magic >> 16) != hw->device_id)
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return -EINVAL;
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- ret_val = i40e_nvmupd_command(hw,
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- (struct i40e_nvm_access *)eeprom,
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- bytes, &errno);
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+ cmd = (struct i40e_nvm_access *)eeprom;
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+ ret_val = i40e_nvmupd_command(hw, cmd, bytes, &errno);
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if (ret_val)
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dev_info(&pf->pdev->dev,
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- "NVMUpdate read failed err=%d status=0x%x\n",
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- ret_val, hw->aq.asq_last_status);
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+ "NVMUpdate read failed err=%d status=0x%x errno=%d module=%d offset=0x%x size=%d\n",
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+ ret_val, hw->aq.asq_last_status, errno,
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+ (u8)(cmd->config & I40E_NVM_MOD_PNT_MASK),
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+ cmd->offset, cmd->data_size);
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return errno;
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}
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@@ -876,20 +878,29 @@ static int i40e_get_eeprom(struct net_device *netdev,
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len = eeprom->len - (I40E_NVM_SECTOR_SIZE * i);
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last = true;
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}
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- ret_val = i40e_aq_read_nvm(hw, 0x0,
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- eeprom->offset + (I40E_NVM_SECTOR_SIZE * i),
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- len,
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+ offset = eeprom->offset + (I40E_NVM_SECTOR_SIZE * i),
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+ ret_val = i40e_aq_read_nvm(hw, 0x0, offset, len,
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(u8 *)eeprom_buff + (I40E_NVM_SECTOR_SIZE * i),
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last, NULL);
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- if (ret_val) {
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+ if (ret_val && hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
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dev_info(&pf->pdev->dev,
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- "read NVM failed err=%d status=0x%x\n",
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- ret_val, hw->aq.asq_last_status);
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- goto release_nvm;
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+ "read NVM failed, invalid offset 0x%x\n",
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+ offset);
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+ break;
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+ } else if (ret_val &&
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+ hw->aq.asq_last_status == I40E_AQ_RC_EACCES) {
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+ dev_info(&pf->pdev->dev,
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+ "read NVM failed, access, offset 0x%x\n",
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+ offset);
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+ break;
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+ } else if (ret_val) {
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+ dev_info(&pf->pdev->dev,
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+ "read NVM failed offset %d err=%d status=0x%x\n",
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+ offset, ret_val, hw->aq.asq_last_status);
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+ break;
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}
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}
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-release_nvm:
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i40e_release_nvm(hw);
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memcpy(bytes, (u8 *)eeprom_buff, eeprom->len);
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free_buff:
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@@ -917,6 +928,7 @@ static int i40e_set_eeprom(struct net_device *netdev,
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struct i40e_netdev_priv *np = netdev_priv(netdev);
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struct i40e_hw *hw = &np->vsi->back->hw;
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struct i40e_pf *pf = np->vsi->back;
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+ struct i40e_nvm_access *cmd;
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int ret_val = 0;
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int errno;
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u32 magic;
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@@ -934,12 +946,14 @@ static int i40e_set_eeprom(struct net_device *netdev,
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test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state))
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return -EBUSY;
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- ret_val = i40e_nvmupd_command(hw, (struct i40e_nvm_access *)eeprom,
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- bytes, &errno);
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- if (ret_val)
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+ cmd = (struct i40e_nvm_access *)eeprom;
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+ ret_val = i40e_nvmupd_command(hw, cmd, bytes, &errno);
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+ if (ret_val && hw->aq.asq_last_status != I40E_AQ_RC_EBUSY)
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dev_info(&pf->pdev->dev,
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- "NVMUpdate write failed err=%d status=0x%x\n",
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- ret_val, hw->aq.asq_last_status);
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+ "NVMUpdate write failed err=%d status=0x%x errno=%d module=%d offset=0x%x size=%d\n",
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+ ret_val, hw->aq.asq_last_status, errno,
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+ (u8)(cmd->config & I40E_NVM_MOD_PNT_MASK),
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+ cmd->offset, cmd->data_size);
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return errno;
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}
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