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@@ -2687,6 +2687,9 @@ void r600_uvd_rbc_stop(struct radeon_device *rdev)
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int r600_uvd_init(struct radeon_device *rdev)
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int r600_uvd_init(struct radeon_device *rdev)
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{
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{
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int i, j, r;
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int i, j, r;
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+ /* disable byte swapping */
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+ u32 lmi_swap_cntl = 0;
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+ u32 mp_swap_cntl = 0;
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/* raise clocks while booting up the VCPU */
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/* raise clocks while booting up the VCPU */
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radeon_set_uvd_clocks(rdev, 53300, 40000);
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radeon_set_uvd_clocks(rdev, 53300, 40000);
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@@ -2711,9 +2714,13 @@ int r600_uvd_init(struct radeon_device *rdev)
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WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
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WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
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(1 << 21) | (1 << 9) | (1 << 20));
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(1 << 21) | (1 << 9) | (1 << 20));
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- /* disable byte swapping */
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- WREG32(UVD_LMI_SWAP_CNTL, 0);
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- WREG32(UVD_MP_SWAP_CNTL, 0);
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+#ifdef __BIG_ENDIAN
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+ /* swap (8 in 32) RB and IB */
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+ lmi_swap_cntl = 0xa;
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+ mp_swap_cntl = 0;
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+#endif
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+ WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);
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+ WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);
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WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
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WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
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WREG32(UVD_MPC_SET_MUXA1, 0x0);
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WREG32(UVD_MPC_SET_MUXA1, 0x0);
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