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@@ -248,18 +248,21 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
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return false;
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}
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+/*
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+ * This calculates a PLL config that will provide the target_clkout rate
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+ * for clkout. Additionally clkdco rate will be the same as clkout rate
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+ * when clkout rate is >= min_clkdco.
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+ */
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bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
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- unsigned long target_tmds, struct dss_pll_clock_info *cinfo)
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+ unsigned long target_clkout, struct dss_pll_clock_info *cinfo)
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{
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unsigned long fint, clkdco, clkout;
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- unsigned long target_bitclk, target_clkdco;
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+ unsigned long target_clkdco;
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unsigned long min_dco;
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unsigned n, m, mf, m2, sd;
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const struct dss_pll_hw *hw = pll->hw;
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- DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds);
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-
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- target_bitclk = target_tmds * 10;
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+ DSSDBG("clkin %lu, target clkout %lu\n", clkin, target_clkout);
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/* Fint */
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n = DIV_ROUND_UP(clkin, hw->fint_max);
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@@ -267,11 +270,11 @@ bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
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/* adjust m2 so that the clkdco will be high enough */
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min_dco = roundup(hw->clkdco_min, fint);
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- m2 = DIV_ROUND_UP(min_dco, target_bitclk);
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+ m2 = DIV_ROUND_UP(min_dco, target_clkout);
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if (m2 == 0)
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m2 = 1;
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- target_clkdco = target_bitclk * m2;
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+ target_clkdco = target_clkout * m2;
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m = target_clkdco / fint;
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clkdco = fint * m;
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