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@@ -378,6 +378,11 @@ struct dmar_domain {
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DECLARE_BITMAP(iommu_bmp, DMAR_UNITS_SUPPORTED);
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DECLARE_BITMAP(iommu_bmp, DMAR_UNITS_SUPPORTED);
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/* bitmap of iommus this domain uses*/
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/* bitmap of iommus this domain uses*/
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+ u16 iommu_did[DMAR_UNITS_SUPPORTED];
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+ /* Domain ids per IOMMU. Use u16 since
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+ * domain ids are 16 bit wide according
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+ * to VT-d spec, section 9.3 */
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+
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struct list_head devices; /* all devices' list */
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struct list_head devices; /* all devices' list */
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struct iova_domain iovad; /* iova's that belong to this domain */
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struct iova_domain iovad; /* iova's that belong to this domain */
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@@ -1543,11 +1548,13 @@ static int iommu_init_domains(struct intel_iommu *iommu)
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}
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}
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/*
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/*
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- * if Caching mode is set, then invalid translations are tagged
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- * with domainid 0. Hence we need to pre-allocate it.
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+ * If Caching mode is set, then invalid translations are tagged
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+ * with domain-id 0, hence we need to pre-allocate it. We also
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+ * use domain-id 0 as a marker for non-allocated domain-id, so
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+ * make sure it is not used for a real domain.
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*/
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*/
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- if (cap_caching_mode(iommu->cap))
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- set_bit(0, iommu->domain_ids);
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+ set_bit(0, iommu->domain_ids);
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+
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return 0;
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return 0;
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}
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}
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@@ -1560,9 +1567,10 @@ static void disable_dmar_iommu(struct intel_iommu *iommu)
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for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
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for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
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/*
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/*
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* Domain id 0 is reserved for invalid translation
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* Domain id 0 is reserved for invalid translation
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- * if hardware supports caching mode.
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+ * if hardware supports caching mode and used as
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+ * a non-allocated marker.
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*/
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*/
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- if (cap_caching_mode(iommu->cap) && i == 0)
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+ if (i == 0)
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continue;
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continue;
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domain = iommu->domains[i];
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domain = iommu->domains[i];
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@@ -1624,6 +1632,7 @@ static int __iommu_attach_domain(struct dmar_domain *domain,
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if (num < ndomains) {
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if (num < ndomains) {
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set_bit(num, iommu->domain_ids);
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set_bit(num, iommu->domain_ids);
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iommu->domains[num] = domain;
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iommu->domains[num] = domain;
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+ domain->iommu_did[iommu->seq_id] = num;
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} else {
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} else {
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num = -ENOSPC;
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num = -ENOSPC;
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}
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}
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@@ -1650,12 +1659,10 @@ static int iommu_attach_vm_domain(struct dmar_domain *domain,
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struct intel_iommu *iommu)
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struct intel_iommu *iommu)
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{
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{
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int num;
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int num;
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- unsigned long ndomains;
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- ndomains = cap_ndoms(iommu->cap);
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- for_each_set_bit(num, iommu->domain_ids, ndomains)
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- if (iommu->domains[num] == domain)
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- return num;
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+ num = domain->iommu_did[iommu->seq_id];
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+ if (num)
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+ return num;
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return __iommu_attach_domain(domain, iommu);
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return __iommu_attach_domain(domain, iommu);
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}
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}
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@@ -1664,22 +1671,18 @@ static void iommu_detach_domain(struct dmar_domain *domain,
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struct intel_iommu *iommu)
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struct intel_iommu *iommu)
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{
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{
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unsigned long flags;
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unsigned long flags;
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- int num, ndomains;
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+ int num;
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spin_lock_irqsave(&iommu->lock, flags);
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spin_lock_irqsave(&iommu->lock, flags);
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- if (domain_type_is_vm_or_si(domain)) {
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- ndomains = cap_ndoms(iommu->cap);
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- for_each_set_bit(num, iommu->domain_ids, ndomains) {
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- if (iommu->domains[num] == domain) {
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- clear_bit(num, iommu->domain_ids);
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- iommu->domains[num] = NULL;
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- break;
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- }
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- }
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- } else {
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- clear_bit(domain->id, iommu->domain_ids);
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- iommu->domains[domain->id] = NULL;
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- }
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+
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+ num = domain->iommu_did[iommu->seq_id];
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+
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+ if (num == 0)
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+ return;
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+
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+ clear_bit(num, iommu->domain_ids);
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+ iommu->domains[num] = NULL;
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+
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spin_unlock_irqrestore(&iommu->lock, flags);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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}
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@@ -1708,6 +1711,7 @@ static int domain_detach_iommu(struct dmar_domain *domain,
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if (test_and_clear_bit(iommu->seq_id, domain->iommu_bmp)) {
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if (test_and_clear_bit(iommu->seq_id, domain->iommu_bmp)) {
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count = --domain->iommu_count;
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count = --domain->iommu_count;
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domain_update_iommu_cap(domain);
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domain_update_iommu_cap(domain);
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+ domain->iommu_did[iommu->seq_id] = 0;
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}
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}
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spin_unlock_irqrestore(&domain->iommu_lock, flags);
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spin_unlock_irqrestore(&domain->iommu_lock, flags);
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