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@@ -20,11 +20,6 @@
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#include <mach/da8xx.h>
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#include <mach/irqs.h>
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-#ifndef CONFIG_COMMON_CLK
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-#include <mach/clock.h>
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-#include "clock.h"
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-#endif
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-
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#define DA8XX_USB0_BASE 0x01e00000
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#define DA8XX_USB1_BASE 0x01e25000
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@@ -87,11 +82,6 @@ static struct platform_device da8xx_usb20_dev = {
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.name = "musb-da8xx",
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.id = -1,
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.dev = {
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- /*
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- * Setting init_name so that clock lookup will work in
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- * usb20_phy_clk_enable() even if this device is not registered.
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- */
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- .init_name = "musb-da8xx",
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.platform_data = &usb_data,
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.dma_mask = &usb_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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@@ -140,234 +130,6 @@ int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata)
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return platform_device_register(&da8xx_usb11_device);
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}
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-#ifndef CONFIG_COMMON_CLK
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-static struct clk usb_refclkin = {
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- .name = "usb_refclkin",
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- .set_rate = davinci_simple_set_rate,
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-};
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-
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-static struct clk_lookup usb_refclkin_lookup =
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- CLK(NULL, "usb_refclkin", &usb_refclkin);
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-
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-/**
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- * da8xx_register_usb_refclkin - register USB_REFCLKIN clock
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- *
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- * @rate: The clock rate in Hz
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- *
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- * This clock is only needed if the board provides an external USB_REFCLKIN
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- * signal, in which case it will be used as the parent of usb20_phy_clk and/or
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- * usb11_phy_clk.
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- */
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-int __init da8xx_register_usb_refclkin(int rate)
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-{
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- int ret;
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-
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- usb_refclkin.rate = rate;
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- ret = clk_register(&usb_refclkin);
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- if (ret)
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- return ret;
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-
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- clkdev_add(&usb_refclkin_lookup);
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-
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- return 0;
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-}
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-
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-static void usb20_phy_clk_enable(struct clk *clk)
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-{
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- u32 val;
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- u32 timeout = 500000; /* 500 msec */
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-
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- val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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-
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- /* The USB 2.O PLL requires that the USB 2.O PSC is enabled as well. */
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- davinci_clk_enable(usb20_clk);
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-
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- /*
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- * Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1
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- * host may use the PLL clock without USB 2.0 OTG being used.
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- */
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- val &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN);
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- val |= CFGCHIP2_PHY_PLLON;
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-
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- writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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-
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- while (--timeout) {
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- val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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- if (val & CFGCHIP2_PHYCLKGD)
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- goto done;
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- udelay(1);
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- }
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-
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- pr_err("Timeout waiting for USB 2.0 PHY clock good\n");
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-done:
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- davinci_clk_disable(usb20_clk);
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-}
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-
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-static void usb20_phy_clk_disable(struct clk *clk)
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-{
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- u32 val;
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-
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- val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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- val |= CFGCHIP2_PHYPWRDN;
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- writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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-}
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-
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-static int usb20_phy_clk_set_parent(struct clk *clk, struct clk *parent)
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-{
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- u32 val;
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-
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- val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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-
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- /* Set the mux depending on the parent clock. */
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- if (parent == &usb_refclkin) {
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- val &= ~CFGCHIP2_USB2PHYCLKMUX;
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- } else if (strcmp(parent->name, "pll0_aux_clk") == 0) {
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- val |= CFGCHIP2_USB2PHYCLKMUX;
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- } else {
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- pr_err("Bad parent on USB 2.0 PHY clock\n");
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- return -EINVAL;
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- }
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-
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- /* reference frequency also comes from parent clock */
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- val &= ~CFGCHIP2_REFFREQ_MASK;
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- switch (clk_get_rate(parent)) {
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- case 12000000:
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- val |= CFGCHIP2_REFFREQ_12MHZ;
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- break;
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- case 13000000:
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- val |= CFGCHIP2_REFFREQ_13MHZ;
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- break;
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- case 19200000:
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- val |= CFGCHIP2_REFFREQ_19_2MHZ;
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- break;
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- case 20000000:
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- val |= CFGCHIP2_REFFREQ_20MHZ;
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- break;
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- case 24000000:
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- val |= CFGCHIP2_REFFREQ_24MHZ;
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- break;
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- case 26000000:
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- val |= CFGCHIP2_REFFREQ_26MHZ;
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- break;
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- case 38400000:
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- val |= CFGCHIP2_REFFREQ_38_4MHZ;
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- break;
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- case 40000000:
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- val |= CFGCHIP2_REFFREQ_40MHZ;
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- break;
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- case 48000000:
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- val |= CFGCHIP2_REFFREQ_48MHZ;
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- break;
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- default:
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- pr_err("Bad parent clock rate on USB 2.0 PHY clock\n");
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- return -EINVAL;
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- }
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-
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- writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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-
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- return 0;
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-}
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-
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-static struct clk usb20_phy_clk = {
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- .name = "usb0_clk48",
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- .clk_enable = usb20_phy_clk_enable,
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- .clk_disable = usb20_phy_clk_disable,
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- .set_parent = usb20_phy_clk_set_parent,
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-};
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-
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-static struct clk_lookup usb20_phy_clk_lookup =
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- CLK("da8xx-usb-phy", "usb0_clk48", &usb20_phy_clk);
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-
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-/**
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- * da8xx_register_usb20_phy_clk - register USB0PHYCLKMUX clock
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- *
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- * @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true
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- * or "pll0_aux" if false.
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- */
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-int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin)
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-{
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- struct clk *parent;
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- int ret;
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-
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- usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20");
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- ret = PTR_ERR_OR_ZERO(usb20_clk);
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- if (ret)
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- return ret;
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-
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- parent = clk_get(NULL, use_usb_refclkin ? "usb_refclkin" : "pll0_aux");
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- ret = PTR_ERR_OR_ZERO(parent);
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- if (ret) {
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- clk_put(usb20_clk);
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- return ret;
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- }
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-
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- usb20_phy_clk.parent = parent;
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- ret = clk_register(&usb20_phy_clk);
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- if (!ret)
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- clkdev_add(&usb20_phy_clk_lookup);
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-
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- clk_put(parent);
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-
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- return ret;
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-}
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-
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-static int usb11_phy_clk_set_parent(struct clk *clk, struct clk *parent)
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-{
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- u32 val;
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-
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- val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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-
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- /* Set the USB 1.1 PHY clock mux based on the parent clock. */
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- if (parent == &usb20_phy_clk) {
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- val &= ~CFGCHIP2_USB1PHYCLKMUX;
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- } else if (parent == &usb_refclkin) {
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- val |= CFGCHIP2_USB1PHYCLKMUX;
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- } else {
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- pr_err("Bad parent on USB 1.1 PHY clock\n");
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- return -EINVAL;
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- }
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-
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- writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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-
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- return 0;
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-}
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-
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-static struct clk usb11_phy_clk = {
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- .name = "usb1_clk48",
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- .set_parent = usb11_phy_clk_set_parent,
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-};
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-
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-static struct clk_lookup usb11_phy_clk_lookup =
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- CLK("da8xx-usb-phy", "usb1_clk48", &usb11_phy_clk);
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-
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-/**
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- * da8xx_register_usb11_phy_clk - register USB1PHYCLKMUX clock
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- *
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- * @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true
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- * or "usb0_clk48" if false.
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- */
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-int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin)
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-{
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- struct clk *parent;
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- int ret = 0;
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-
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- if (use_usb_refclkin)
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- parent = clk_get(NULL, "usb_refclkin");
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- else
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- parent = clk_get(&da8xx_usb_phy.dev, "usb0_clk48");
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- if (IS_ERR(parent))
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- return PTR_ERR(parent);
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-
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- usb11_phy_clk.parent = parent;
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- ret = clk_register(&usb11_phy_clk);
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- if (!ret)
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- clkdev_add(&usb11_phy_clk_lookup);
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-
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- clk_put(parent);
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-
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- return ret;
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-}
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-#endif
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static struct platform_device da8xx_usb_phy_clks_device = {
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.name = "da830-usb-phy-clks",
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.id = -1,
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