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@@ -106,26 +106,24 @@ void __init imx_init_l2cache(void)
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goto out;
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goto out;
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}
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}
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- if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)
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- goto skip_if_enabled;
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-
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- /* Configure the L2 PREFETCH and POWER registers */
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- val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
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- val |= 0x70800000;
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- /*
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- * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
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- * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
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- * But according to ARM PL310 errata: 752271
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- * ID: 752271: Double linefill feature can cause data corruption
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- * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
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- * Workaround: The only workaround to this erratum is to disable the
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- * double linefill feature. This is the default behavior.
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- */
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- if (cpu_is_imx6q())
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- val &= ~(1 << 30 | 1 << 23);
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- writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
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+ if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
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+ /* Configure the L2 PREFETCH and POWER registers */
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+ val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
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+ val |= 0x70800000;
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+ /*
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+ * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
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+ * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
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+ * But according to ARM PL310 errata: 752271
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+ * ID: 752271: Double linefill feature can cause data corruption
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+ * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
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+ * Workaround: The only workaround to this erratum is to disable the
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+ * double linefill feature. This is the default behavior.
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+ */
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+ if (cpu_is_imx6q())
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+ val &= ~(1 << 30 | 1 << 23);
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+ writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
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+ }
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-skip_if_enabled:
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iounmap(l2x0_base);
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iounmap(l2x0_base);
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of_node_put(np);
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of_node_put(np);
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