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@@ -77,13 +77,13 @@
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#define OV13858_ANA_GAIN_DEFAULT 0x80
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/* Digital gain control */
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-#define OV13858_REG_DIGITAL_GAIN 0x350a
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-#define OV13858_DGTL_GAIN_MASK 0xf3
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-#define OV13858_DGTL_GAIN_SHIFT 2
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-#define OV13858_DGTL_GAIN_MIN 1
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-#define OV13858_DGTL_GAIN_MAX 4
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-#define OV13858_DGTL_GAIN_STEP 1
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-#define OV13858_DGTL_GAIN_DEFAULT 1
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+#define OV13858_REG_B_MWB_GAIN 0x5100
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+#define OV13858_REG_G_MWB_GAIN 0x5102
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+#define OV13858_REG_R_MWB_GAIN 0x5104
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+#define OV13858_DGTL_GAIN_MIN 0
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+#define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */
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+#define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */
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+#define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
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/* Test Pattern Control */
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#define OV13858_REG_TEST_PATTERN 0x4503
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@@ -1162,21 +1162,21 @@ static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
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static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
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{
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int ret;
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- u32 val;
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- if (d_gain == 3)
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- return -EINVAL;
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+ ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN,
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+ OV13858_REG_VALUE_16BIT, d_gain);
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+ if (ret)
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+ return ret;
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- ret = ov13858_read_reg(ov13858, OV13858_REG_DIGITAL_GAIN,
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- OV13858_REG_VALUE_08BIT, &val);
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+ ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN,
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+ OV13858_REG_VALUE_16BIT, d_gain);
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if (ret)
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return ret;
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- val &= OV13858_DGTL_GAIN_MASK;
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- val |= (d_gain - 1) << OV13858_DGTL_GAIN_SHIFT;
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+ ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN,
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+ OV13858_REG_VALUE_16BIT, d_gain);
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- return ov13858_write_reg(ov13858, OV13858_REG_DIGITAL_GAIN,
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- OV13858_REG_VALUE_08BIT, val);
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+ return ret;
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}
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static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)
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