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@@ -0,0 +1,23 @@
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+Xilinx Axi Uartlite controller Device Tree Bindings
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+---------------------------------------------------------
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+
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+Required properties:
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+- compatible : Can be either of
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+ "xlnx,xps-uartlite-1.00.a"
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+ "xlnx,opb-uartlite-1.00.b"
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+- reg : Physical base address and size of the Axi Uartlite
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+ registers map.
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+- interrupts : Should contain the UART controller interrupt.
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+
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+Optional properties:
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+- port-number : Set Uart port number
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+- clock-names : Should be "s_axi_aclk"
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+- clocks : Input clock specifier. Refer to common clock bindings.
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+
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+Example:
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+serial@800c0000 {
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+ compatible = "xlnx,xps-uartlite-1.00.a";
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+ reg = <0x0 0x800c0000 0x10000>;
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+ interrupts = <0x0 0x6e 0x1>;
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+ port-number = <0>;
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+};
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