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@@ -12,7 +12,8 @@
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* HW only supports 7 predefined pixel clocks, and clock select is
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* in bit 29:27 of Display Control register.
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*/
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-static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, unsigned long dispControl)
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+static unsigned long displayControlAdjust_SM750LE(struct mode_parameter *pModeParam,
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+ unsigned long dispControl)
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{
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unsigned long x, y;
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@@ -72,7 +73,8 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam,
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}
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/* only timing related registers will be programed */
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-static int programModeRegisters(mode_parameter_t *pModeParam, struct pll_value *pll)
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+static int programModeRegisters(struct mode_parameter *pModeParam,
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+ struct pll_value *pll)
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{
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int ret = 0;
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int cnt = 0;
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@@ -203,7 +205,7 @@ static int programModeRegisters(mode_parameter_t *pModeParam, struct pll_value *
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return ret;
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}
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-int ddk750_setModeTiming(mode_parameter_t *parm, clock_type_t clock)
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+int ddk750_setModeTiming(struct mode_parameter *parm, clock_type_t clock)
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{
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struct pll_value pll;
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unsigned int uiActualPixelClk;
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