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@@ -501,17 +501,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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cmpwi r0, 0
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beq 57f
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li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
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- mfspr r4, SPRN_LPCR
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- rlwimi r4, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
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- mtspr SPRN_LPCR, r4
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- isync
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- std r0, HSTATE_SCRATCH0(r13)
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- ptesync
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- ld r0, HSTATE_SCRATCH0(r13)
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-1: cmpd r0, r0
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- bne 1b
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- nap
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- b .
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+ mfspr r5, SPRN_LPCR
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+ rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
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+ b kvm_nap_sequence
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57: li r0, 0
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stbx r0, r3, r4
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@@ -2256,6 +2248,21 @@ BEGIN_FTR_SECTION
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ori r5, r5, LPCR_PECEDH
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rlwimi r5, r3, 0, LPCR_PECEDP
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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+
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+kvm_nap_sequence: /* desired LPCR value in r5 */
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+BEGIN_FTR_SECTION
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+ /*
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+ * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
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+ * enable state loss = 1 (allow SMT mode switch)
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+ * requested level = 0 (just stop dispatching)
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+ */
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+ lis r3, (PSSCR_EC | PSSCR_ESL)@h
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+ mtspr SPRN_PSSCR, r3
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+ /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
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+ li r4, LPCR_PECE_HVEE@higher
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+ sldi r4, r4, 32
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+ or r5, r5, r4
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+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
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mtspr SPRN_LPCR,r5
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isync
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li r0, 0
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@@ -2264,7 +2271,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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ld r0, HSTATE_SCRATCH0(r13)
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1: cmpd r0, r0
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bne 1b
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+BEGIN_FTR_SECTION
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nap
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+FTR_SECTION_ELSE
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+ PPC_STOP
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+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
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b .
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33: mr r4, r3
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