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@@ -543,7 +543,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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int err, i;
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u32 status;
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- gpiod_set_value(rockchip->ep_gpio, 0);
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+ gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
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err = reset_control_assert(rockchip->aclk_rst);
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if (err) {
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@@ -688,7 +688,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
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PCIE_CLIENT_CONFIG);
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- gpiod_set_value(rockchip->ep_gpio, 1);
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+ gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
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/* 500ms timeout value should be enough for Gen1/2 training */
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err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
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