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@@ -1321,12 +1321,19 @@ MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
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*/
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MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
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-static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
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+/* reg_slcr_seed
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+ * LAG seed value. The seed is the same for all ports.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
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+
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+static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
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{
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MLXSW_REG_ZERO(slcr, payload);
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mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
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mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
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mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
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+ mlxsw_reg_slcr_seed_set(payload, seed);
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}
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/* SLCOR - Switch LAG Collector Register
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