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@@ -1828,8 +1828,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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u32 saveLedState;
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u32 saveDefAntenna;
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u32 macStaId1;
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+ struct timespec tsf_ts;
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+ u32 tsf_offset;
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u64 tsf = 0;
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- s64 usec = 0;
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int r;
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bool start_mci_reset = false;
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bool save_fullsleep = ah->chip_fullsleep;
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@@ -1873,8 +1874,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
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/* Save TSF before chip reset, a cold reset clears it */
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+ getrawmonotonic(&tsf_ts);
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tsf = ath9k_hw_gettsf64(ah);
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- usec = ktime_to_us(ktime_get_raw());
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saveLedState = REG_READ(ah, AR_CFG_LED) &
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(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
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@@ -1907,8 +1908,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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}
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/* Restore TSF */
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- usec = ktime_to_us(ktime_get_raw()) - usec;
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- ath9k_hw_settsf64(ah, tsf + usec);
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+ tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
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+ ath9k_hw_settsf64(ah, tsf + tsf_offset);
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if (AR_SREV_9280_20_OR_LATER(ah))
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REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
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@@ -1928,12 +1929,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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/*
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* Some AR91xx SoC devices frequently fail to accept TSF writes
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* right after the chip reset. When that happens, write a new
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- * value after the initvals have been applied, with an offset
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- * based on measured time difference
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+ * value after the initvals have been applied.
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*/
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if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
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- tsf += 1500;
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- ath9k_hw_settsf64(ah, tsf);
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+ tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
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+ ath9k_hw_settsf64(ah, tsf + tsf_offset);
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}
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ath9k_hw_init_mfp(ah);
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