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@@ -287,7 +287,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
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send the minimal TP1 possible and skip TP2. */
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send the minimal TP1 possible and skip TP2. */
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val |= EDP_PSR_TP1_TIME_100us;
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val |= EDP_PSR_TP1_TIME_100us;
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val |= EDP_PSR_TP2_TP3_TIME_0us;
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val |= EDP_PSR_TP2_TP3_TIME_0us;
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- val |= EDP_PSR_SKIP_AUX_EXIT;
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/* Sink should be able to train with the 5 or 6 idle patterns */
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/* Sink should be able to train with the 5 or 6 idle patterns */
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idle_frames += 4;
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idle_frames += 4;
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}
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}
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