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+/*
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+ * Copyright 2012 Red Hat Inc.
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ *
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+ * Authors: Ben Skeggs
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+ */
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+#define gp100_mc(p) container_of((p), struct gp100_mc, base)
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+#include "priv.h"
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+
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+struct gp100_mc {
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+ struct nvkm_mc base;
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+ spinlock_t lock;
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+ bool intr;
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+ u32 mask;
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+};
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+
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+static void
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+gp100_mc_intr_update(struct gp100_mc *mc)
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+{
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+ struct nvkm_device *device = mc->base.subdev.device;
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+ u32 mask = mc->intr ? mc->mask : 0, i;
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+ for (i = 0; i < 2; i++) {
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+ nvkm_wr32(device, 0x000180 + (i * 0x04), ~mask);
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+ nvkm_wr32(device, 0x000160 + (i * 0x04), mask);
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+ }
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+}
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+
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+static void
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+gp100_mc_intr_unarm(struct nvkm_mc *base)
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+{
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+ struct gp100_mc *mc = gp100_mc(base);
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+ unsigned long flags;
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+ spin_lock_irqsave(&mc->lock, flags);
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+ mc->intr = false;
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+ gp100_mc_intr_update(mc);
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+ spin_unlock_irqrestore(&mc->lock, flags);
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+}
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+
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+static void
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+gp100_mc_intr_rearm(struct nvkm_mc *base)
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+{
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+ struct gp100_mc *mc = gp100_mc(base);
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+ unsigned long flags;
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+ spin_lock_irqsave(&mc->lock, flags);
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+ mc->intr = true;
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+ gp100_mc_intr_update(mc);
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+ spin_unlock_irqrestore(&mc->lock, flags);
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+}
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+
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+static void
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+gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr)
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+{
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+ struct gp100_mc *mc = gp100_mc(base);
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+ unsigned long flags;
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+ spin_lock_irqsave(&mc->lock, flags);
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+ mc->mask = (mc->mask & ~mask) | intr;
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+ gp100_mc_intr_update(mc);
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+ spin_unlock_irqrestore(&mc->lock, flags);
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+}
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+
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+static const struct nvkm_mc_func
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+gp100_mc = {
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+ .init = nv50_mc_init,
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+ .intr = gk104_mc_intr,
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+ .intr_unarm = gp100_mc_intr_unarm,
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+ .intr_rearm = gp100_mc_intr_rearm,
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+ .intr_mask = gp100_mc_intr_mask,
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+ .intr_stat = gf100_mc_intr_stat,
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+ .reset = gk104_mc_reset,
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+};
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+
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+int
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+gp100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
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+{
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+ struct gp100_mc *mc;
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+
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+ if (!(mc = kzalloc(sizeof(*mc), GFP_KERNEL)))
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+ return -ENOMEM;
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+ nvkm_mc_ctor(&gp100_mc, device, index, &mc->base);
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+ *pmc = &mc->base;
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+
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+ spin_lock_init(&mc->lock);
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+ mc->intr = false;
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+ mc->mask = 0x7fffffff;
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+ return 0;
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+}
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