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@@ -0,0 +1,567 @@
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+/*
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+ * Faraday Technology FTIDE010 driver
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+ * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
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+ *
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+ * Includes portions of the SL2312/SL3516/Gemini PATA driver
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+ * Copyright (C) 2003 StorLine, Inc <jason@storlink.com.tw>
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+ * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
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+ * Copyright (C) 2010 Frederic Pecourt <opengemini@free.fr>
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+ * Copyright (C) 2011 Tobias Waldvogel <tobias.waldvogel@gmail.com>
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+ */
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+
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+#include <linux/platform_device.h>
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+#include <linux/module.h>
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+#include <linux/libata.h>
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+#include <linux/bitops.h>
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+#include <linux/of_address.h>
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+#include <linux/of_device.h>
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+#include <linux/clk.h>
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+#include "sata_gemini.h"
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+
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+#define DRV_NAME "pata_ftide010"
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+
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+/**
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+ * struct ftide010 - state container for the Faraday FTIDE010
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+ * @dev: pointer back to the device representing this controller
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+ * @base: remapped I/O space address
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+ * @pclk: peripheral clock for the IDE block
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+ * @host: pointer to the ATA host for this device
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+ * @master_cbl: master cable type
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+ * @slave_cbl: slave cable type
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+ * @sg: Gemini SATA bridge pointer, if running on the Gemini
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+ * @master_to_sata0: Gemini SATA bridge: the ATA master is connected
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+ * to the SATA0 bridge
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+ * @slave_to_sata0: Gemini SATA bridge: the ATA slave is connected
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+ * to the SATA0 bridge
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+ * @master_to_sata1: Gemini SATA bridge: the ATA master is connected
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+ * to the SATA1 bridge
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+ * @slave_to_sata1: Gemini SATA bridge: the ATA slave is connected
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+ * to the SATA1 bridge
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+ */
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+struct ftide010 {
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+ struct device *dev;
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+ void __iomem *base;
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+ struct clk *pclk;
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+ struct ata_host *host;
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+ unsigned int master_cbl;
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+ unsigned int slave_cbl;
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+ /* Gemini-specific properties */
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+ struct sata_gemini *sg;
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+ bool master_to_sata0;
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+ bool slave_to_sata0;
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+ bool master_to_sata1;
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+ bool slave_to_sata1;
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+};
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+
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+#define FTIDE010_DMA_REG 0x00
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+#define FTIDE010_DMA_STATUS 0x02
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+#define FTIDE010_IDE_BMDTPR 0x04
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+#define FTIDE010_IDE_DEVICE_ID 0x08
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+#define FTIDE010_PIO_TIMING 0x10
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+#define FTIDE010_MWDMA_TIMING 0x11
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+#define FTIDE010_UDMA_TIMING0 0x12 /* Master */
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+#define FTIDE010_UDMA_TIMING1 0x13 /* Slave */
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+#define FTIDE010_CLK_MOD 0x14
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+/* These registers are mapped directly to the IDE registers */
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+#define FTIDE010_CMD_DATA 0x20
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+#define FTIDE010_ERROR_FEATURES 0x21
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+#define FTIDE010_NSECT 0x22
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+#define FTIDE010_LBAL 0x23
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+#define FTIDE010_LBAM 0x24
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+#define FTIDE010_LBAH 0x25
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+#define FTIDE010_DEVICE 0x26
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+#define FTIDE010_STATUS_COMMAND 0x27
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+#define FTIDE010_ALTSTAT_CTRL 0x36
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+
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+/* Set this bit for UDMA mode 5 and 6 */
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+#define FTIDE010_UDMA_TIMING_MODE_56 BIT(7)
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+
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+/* 0 = 50 MHz, 1 = 66 MHz */
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+#define FTIDE010_CLK_MOD_DEV0_CLK_SEL BIT(0)
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+#define FTIDE010_CLK_MOD_DEV1_CLK_SEL BIT(1)
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+/* Enable UDMA on a device */
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+#define FTIDE010_CLK_MOD_DEV0_UDMA_EN BIT(4)
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+#define FTIDE010_CLK_MOD_DEV1_UDMA_EN BIT(5)
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+
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+static struct scsi_host_template pata_ftide010_sht = {
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+ ATA_BMDMA_SHT(DRV_NAME),
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+};
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+
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+/*
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+ * Bus timings
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+ *
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+ * The unit of the below required timings is two clock periods of the ATA
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+ * reference clock which is 30 nanoseconds per unit at 66MHz and 20
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+ * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
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+ * PIO.
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+ *
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+ * pio_active_time: array of 5 elements for T2 timing for Mode 0,
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+ * 1, 2, 3 and 4. Range 0..15.
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+ * pio_recovery_time: array of 5 elements for T2l timing for Mode 0,
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+ * 1, 2, 3 and 4. Range 0..15.
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+ * mdma_50_active_time: array of 4 elements for Td timing for multi
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+ * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
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+ * mdma_50_recovery_time: array of 4 elements for Tk timing for
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+ * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
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+ * mdma_66_active_time: array of 4 elements for Td timing for multi
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+ * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
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+ * mdma_66_recovery_time: array of 4 elements for Tk timing for
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+ * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
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+ * udma_50_setup_time: array of 4 elements for Tvds timing for ultra
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+ * DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7.
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+ * udma_50_hold_time: array of 4 elements for Tdvh timing for
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+ * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
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+ * udma_66_setup_time: array of 4 elements for Tvds timing for multi
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+ * word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
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+ * udma_66_hold_time: array of 4 elements for Tdvh timing for
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+ * multi word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
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+ */
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+static const u8 pio_active_time[5] = {10, 10, 10, 3, 3};
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+static const u8 pio_recovery_time[5] = {10, 3, 1, 3, 1};
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+static const u8 mwdma_50_active_time[3] = {6, 2, 2};
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+static const u8 mwdma_50_recovery_time[3] = {6, 2, 1};
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+static const u8 mwdma_66_active_time[3] = {8, 3, 3};
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+static const u8 mwdma_66_recovery_time[3] = {8, 2, 1};
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+static const u8 udma_50_setup_time[6] = {3, 3, 2, 2, 1, 1};
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+static const u8 udma_50_hold_time[6] = {3, 1, 1, 1, 1, 1};
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+static const u8 udma_66_setup_time[7] = {4, 4, 3, 2, };
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+static const u8 udma_66_hold_time[7] = {};
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+
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+/*
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+ * We set 66 MHz for all MWDMA modes
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+ */
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+static const bool set_mdma_66_mhz[] = { true, true, true, true };
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+
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+/*
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+ * We set 66 MHz for UDMA modes 3, 4 and 6 and no others
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+ */
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+static const bool set_udma_66_mhz[] = { false, false, false, true, true, false, true };
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+
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+static void ftide010_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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+{
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+ struct ftide010 *ftide = ap->host->private_data;
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+ u8 speed = adev->dma_mode;
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+ u8 devno = adev->devno & 1;
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+ u8 udma_en_mask;
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+ u8 f66m_en_mask;
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+ u8 clkreg;
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+ u8 timreg;
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+ u8 i;
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+
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+ /* Target device 0 (master) or 1 (slave) */
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+ if (!devno) {
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+ udma_en_mask = FTIDE010_CLK_MOD_DEV0_UDMA_EN;
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+ f66m_en_mask = FTIDE010_CLK_MOD_DEV0_CLK_SEL;
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+ } else {
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+ udma_en_mask = FTIDE010_CLK_MOD_DEV1_UDMA_EN;
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+ f66m_en_mask = FTIDE010_CLK_MOD_DEV1_CLK_SEL;
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+ }
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+
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+ clkreg = readb(ftide->base + FTIDE010_CLK_MOD);
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+ clkreg &= ~udma_en_mask;
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+ clkreg &= ~f66m_en_mask;
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+
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+ if (speed & XFER_UDMA_0) {
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+ i = speed & ~XFER_UDMA_0;
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+ dev_dbg(ftide->dev, "set UDMA mode %02x, index %d\n",
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+ speed, i);
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+
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+ clkreg |= udma_en_mask;
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+ if (set_udma_66_mhz[i]) {
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+ clkreg |= f66m_en_mask;
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+ timreg = udma_66_setup_time[i] << 4 |
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+ udma_66_hold_time[i];
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+ } else {
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+ timreg = udma_50_setup_time[i] << 4 |
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+ udma_50_hold_time[i];
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+ }
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+
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+ /* A special bit needs to be set for modes 5 and 6 */
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+ if (i >= 5)
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+ timreg |= FTIDE010_UDMA_TIMING_MODE_56;
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+
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+ dev_dbg(ftide->dev, "UDMA write clkreg = %02x, timreg = %02x\n",
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+ clkreg, timreg);
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+
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+ writeb(clkreg, ftide->base + FTIDE010_CLK_MOD);
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+ writeb(timreg, ftide->base + FTIDE010_UDMA_TIMING0 + devno);
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+ } else {
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+ i = speed & ~XFER_MW_DMA_0;
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+ dev_dbg(ftide->dev, "set MWDMA mode %02x, index %d\n",
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+ speed, i);
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+
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+ if (set_mdma_66_mhz[i]) {
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+ clkreg |= f66m_en_mask;
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+ timreg = mwdma_66_active_time[i] << 4 |
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+ mwdma_66_recovery_time[i];
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+ } else {
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+ timreg = mwdma_50_active_time[i] << 4 |
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+ mwdma_50_recovery_time[i];
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+ }
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+ dev_dbg(ftide->dev,
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+ "MWDMA write clkreg = %02x, timreg = %02x\n",
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+ clkreg, timreg);
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+ /* This will affect all devices */
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+ writeb(clkreg, ftide->base + FTIDE010_CLK_MOD);
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+ writeb(timreg, ftide->base + FTIDE010_MWDMA_TIMING);
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+ }
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+
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+ /*
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+ * Store the current device (master or slave) in ap->private_data
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+ * so that .qc_issue() can detect if this changes and reprogram
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+ * the DMA settings.
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+ */
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+ ap->private_data = adev;
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+
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+ return;
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+}
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+
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+static void ftide010_set_piomode(struct ata_port *ap, struct ata_device *adev)
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+{
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+ struct ftide010 *ftide = ap->host->private_data;
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+ u8 pio = adev->pio_mode - XFER_PIO_0;
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+
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+ dev_dbg(ftide->dev, "set PIO mode %02x, index %d\n",
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+ adev->pio_mode, pio);
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+ writeb(pio_active_time[pio] << 4 | pio_recovery_time[pio],
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+ ftide->base + FTIDE010_PIO_TIMING);
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+}
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+
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+/*
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+ * We implement our own qc_issue() callback since we may need to set up
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+ * the timings differently for master and slave transfers: the CLK_MOD_REG
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+ * and MWDMA_TIMING_REG is shared between master and slave, so reprogramming
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+ * this may be necessary.
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+ */
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+static unsigned int ftide010_qc_issue(struct ata_queued_cmd *qc)
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+{
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+ struct ata_port *ap = qc->ap;
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+ struct ata_device *adev = qc->dev;
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+
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+ /*
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+ * If the device changed, i.e. slave->master, master->slave,
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+ * then set up the DMA mode again so we are sure the timings
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+ * are correct.
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+ */
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+ if (adev != ap->private_data && ata_dma_enabled(adev))
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+ ftide010_set_dmamode(ap, adev);
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+
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+ return ata_bmdma_qc_issue(qc);
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+}
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+
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+static struct ata_port_operations pata_ftide010_port_ops = {
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+ .inherits = &ata_bmdma_port_ops,
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+ .set_dmamode = ftide010_set_dmamode,
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+ .set_piomode = ftide010_set_piomode,
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+ .qc_issue = ftide010_qc_issue,
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+};
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+
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+static struct ata_port_info ftide010_port_info[] = {
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+ {
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+ .flags = ATA_FLAG_SLAVE_POSS,
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+ .mwdma_mask = ATA_MWDMA2,
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+ .udma_mask = ATA_UDMA6,
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+ .pio_mask = ATA_PIO4,
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+ .port_ops = &pata_ftide010_port_ops,
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+ },
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+};
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+
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+#if IS_ENABLED(CONFIG_SATA_GEMINI)
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+
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+static int pata_ftide010_gemini_port_start(struct ata_port *ap)
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+{
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+ struct ftide010 *ftide = ap->host->private_data;
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+ struct device *dev = ftide->dev;
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+ struct sata_gemini *sg = ftide->sg;
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+ int bridges = 0;
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+ int ret;
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+
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+ ret = ata_bmdma_port_start(ap);
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+ if (ret)
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+ return ret;
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+
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+ if (ftide->master_to_sata0) {
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+ dev_info(dev, "SATA0 (master) start\n");
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+ ret = gemini_sata_start_bridge(sg, 0);
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+ if (!ret)
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+ bridges++;
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+ }
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+ if (ftide->master_to_sata1) {
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+ dev_info(dev, "SATA1 (master) start\n");
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+ ret = gemini_sata_start_bridge(sg, 1);
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+ if (!ret)
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+ bridges++;
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+ }
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+ /* Avoid double-starting */
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+ if (ftide->slave_to_sata0 && !ftide->master_to_sata0) {
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+ dev_info(dev, "SATA0 (slave) start\n");
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+ ret = gemini_sata_start_bridge(sg, 0);
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+ if (!ret)
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+ bridges++;
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+ }
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+ /* Avoid double-starting */
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+ if (ftide->slave_to_sata1 && !ftide->master_to_sata1) {
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+ dev_info(dev, "SATA1 (slave) start\n");
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+ ret = gemini_sata_start_bridge(sg, 1);
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+ if (!ret)
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+ bridges++;
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+ }
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+
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+ dev_info(dev, "brought %d bridges online\n", bridges);
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+ return (bridges > 0) ? 0 : -EINVAL; // -ENODEV;
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+}
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+
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+static void pata_ftide010_gemini_port_stop(struct ata_port *ap)
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+{
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+ struct ftide010 *ftide = ap->host->private_data;
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+ struct device *dev = ftide->dev;
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+ struct sata_gemini *sg = ftide->sg;
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+
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+ if (ftide->master_to_sata0) {
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+ dev_info(dev, "SATA0 (master) stop\n");
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+ gemini_sata_stop_bridge(sg, 0);
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+ }
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+ if (ftide->master_to_sata1) {
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+ dev_info(dev, "SATA1 (master) stop\n");
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+ gemini_sata_stop_bridge(sg, 1);
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+ }
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+ /* Avoid double-stopping */
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+ if (ftide->slave_to_sata0 && !ftide->master_to_sata0) {
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+ dev_info(dev, "SATA0 (slave) stop\n");
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+ gemini_sata_stop_bridge(sg, 0);
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+ }
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+ /* Avoid double-stopping */
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+ if (ftide->slave_to_sata1 && !ftide->master_to_sata1) {
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+ dev_info(dev, "SATA1 (slave) stop\n");
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+ gemini_sata_stop_bridge(sg, 1);
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+ }
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+}
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+
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+static int pata_ftide010_gemini_cable_detect(struct ata_port *ap)
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+{
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+ struct ftide010 *ftide = ap->host->private_data;
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+
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+ /*
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+ * Return the master cable, I have no clue how to return a different
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+ * cable for the slave than for the master.
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+ */
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+ return ftide->master_cbl;
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+}
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+
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+static int pata_ftide010_gemini_init(struct ftide010 *ftide,
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+ bool is_ata1)
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+{
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+ struct device *dev = ftide->dev;
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+ struct sata_gemini *sg;
|
|
|
+ enum gemini_muxmode muxmode;
|
|
|
+
|
|
|
+ /* Look up SATA bridge */
|
|
|
+ sg = gemini_sata_bridge_get();
|
|
|
+ if (IS_ERR(sg))
|
|
|
+ return PTR_ERR(sg);
|
|
|
+ ftide->sg = sg;
|
|
|
+
|
|
|
+ muxmode = gemini_sata_get_muxmode(sg);
|
|
|
+
|
|
|
+ /* Special ops */
|
|
|
+ pata_ftide010_port_ops.port_start =
|
|
|
+ pata_ftide010_gemini_port_start;
|
|
|
+ pata_ftide010_port_ops.port_stop =
|
|
|
+ pata_ftide010_gemini_port_stop;
|
|
|
+ pata_ftide010_port_ops.cable_detect =
|
|
|
+ pata_ftide010_gemini_cable_detect;
|
|
|
+
|
|
|
+ /* Flag port as SATA-capable */
|
|
|
+ if (gemini_sata_bridge_enabled(sg, is_ata1))
|
|
|
+ ftide010_port_info[0].flags |= ATA_FLAG_SATA;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * We assume that a simple 40-wire cable is used in the PATA mode.
|
|
|
+ * if you're adding a system using the PATA interface, make sure
|
|
|
+ * the right cable is set up here, it might be necessary to use
|
|
|
+ * special hardware detection or encode the cable type in the device
|
|
|
+ * tree with special properties.
|
|
|
+ */
|
|
|
+ if (!is_ata1) {
|
|
|
+ switch (muxmode) {
|
|
|
+ case GEMINI_MUXMODE_0:
|
|
|
+ ftide->master_cbl = ATA_CBL_SATA;
|
|
|
+ ftide->slave_cbl = ATA_CBL_PATA40;
|
|
|
+ ftide->master_to_sata0 = true;
|
|
|
+ break;
|
|
|
+ case GEMINI_MUXMODE_1:
|
|
|
+ ftide->master_cbl = ATA_CBL_SATA;
|
|
|
+ ftide->slave_cbl = ATA_CBL_NONE;
|
|
|
+ ftide->master_to_sata0 = true;
|
|
|
+ break;
|
|
|
+ case GEMINI_MUXMODE_2:
|
|
|
+ ftide->master_cbl = ATA_CBL_PATA40;
|
|
|
+ ftide->slave_cbl = ATA_CBL_PATA40;
|
|
|
+ break;
|
|
|
+ case GEMINI_MUXMODE_3:
|
|
|
+ ftide->master_cbl = ATA_CBL_SATA;
|
|
|
+ ftide->slave_cbl = ATA_CBL_SATA;
|
|
|
+ ftide->master_to_sata0 = true;
|
|
|
+ ftide->slave_to_sata1 = true;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ switch (muxmode) {
|
|
|
+ case GEMINI_MUXMODE_0:
|
|
|
+ ftide->master_cbl = ATA_CBL_SATA;
|
|
|
+ ftide->slave_cbl = ATA_CBL_NONE;
|
|
|
+ ftide->master_to_sata1 = true;
|
|
|
+ break;
|
|
|
+ case GEMINI_MUXMODE_1:
|
|
|
+ ftide->master_cbl = ATA_CBL_SATA;
|
|
|
+ ftide->slave_cbl = ATA_CBL_PATA40;
|
|
|
+ ftide->master_to_sata1 = true;
|
|
|
+ break;
|
|
|
+ case GEMINI_MUXMODE_2:
|
|
|
+ ftide->master_cbl = ATA_CBL_SATA;
|
|
|
+ ftide->slave_cbl = ATA_CBL_SATA;
|
|
|
+ ftide->slave_to_sata0 = true;
|
|
|
+ ftide->master_to_sata1 = true;
|
|
|
+ break;
|
|
|
+ case GEMINI_MUXMODE_3:
|
|
|
+ ftide->master_cbl = ATA_CBL_PATA40;
|
|
|
+ ftide->slave_cbl = ATA_CBL_PATA40;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ dev_info(dev, "set up Gemini PATA%d\n", is_ata1);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+#else
|
|
|
+static int pata_ftide010_gemini_init(struct ftide010 *ftide,
|
|
|
+ bool is_ata1)
|
|
|
+{
|
|
|
+ return -ENOTSUPP;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+
|
|
|
+static int pata_ftide010_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
+ struct device_node *np = dev->of_node;
|
|
|
+ const struct ata_port_info pi = ftide010_port_info[0];
|
|
|
+ const struct ata_port_info *ppi[] = { &pi, NULL };
|
|
|
+ struct ftide010 *ftide;
|
|
|
+ struct resource *res;
|
|
|
+ int irq;
|
|
|
+ int ret;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ ftide = devm_kzalloc(dev, sizeof(*ftide), GFP_KERNEL);
|
|
|
+ if (!ftide)
|
|
|
+ return -ENOMEM;
|
|
|
+ ftide->dev = dev;
|
|
|
+
|
|
|
+ irq = platform_get_irq(pdev, 0);
|
|
|
+ if (irq < 0)
|
|
|
+ return irq;
|
|
|
+
|
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
+ if (!res)
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ ftide->base = devm_ioremap_resource(dev, res);
|
|
|
+ if (IS_ERR(ftide->base))
|
|
|
+ return PTR_ERR(ftide->base);
|
|
|
+
|
|
|
+ ftide->pclk = devm_clk_get(dev, "PCLK");
|
|
|
+ if (!IS_ERR(ftide->pclk)) {
|
|
|
+ ret = clk_prepare_enable(ftide->pclk);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "failed to enable PCLK\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Some special Cortina Gemini init, if needed */
|
|
|
+ if (of_device_is_compatible(np, "cortina,gemini-pata")) {
|
|
|
+ /*
|
|
|
+ * We need to know which instance is probing (the
|
|
|
+ * Gemini has two instances of FTIDE010) and we do
|
|
|
+ * this simply by looking at the physical base
|
|
|
+ * address, which is 0x63400000 for ATA1, else we
|
|
|
+ * are ATA0. This will also set up the cable types.
|
|
|
+ */
|
|
|
+ ret = pata_ftide010_gemini_init(ftide,
|
|
|
+ (res->start == 0x63400000));
|
|
|
+ if (ret)
|
|
|
+ goto err_dis_clk;
|
|
|
+ } else {
|
|
|
+ /* Else assume we are connected using PATA40 */
|
|
|
+ ftide->master_cbl = ATA_CBL_PATA40;
|
|
|
+ ftide->slave_cbl = ATA_CBL_PATA40;
|
|
|
+ }
|
|
|
+
|
|
|
+ ftide->host = ata_host_alloc_pinfo(dev, ppi, 1);
|
|
|
+ if (!ftide->host) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto err_dis_clk;
|
|
|
+ }
|
|
|
+ ftide->host->private_data = ftide;
|
|
|
+
|
|
|
+ for (i = 0; i < ftide->host->n_ports; i++) {
|
|
|
+ struct ata_port *ap = ftide->host->ports[i];
|
|
|
+ struct ata_ioports *ioaddr = &ap->ioaddr;
|
|
|
+
|
|
|
+ ioaddr->bmdma_addr = ftide->base + FTIDE010_DMA_REG;
|
|
|
+ ioaddr->cmd_addr = ftide->base + FTIDE010_CMD_DATA;
|
|
|
+ ioaddr->ctl_addr = ftide->base + FTIDE010_ALTSTAT_CTRL;
|
|
|
+ ioaddr->altstatus_addr = ftide->base + FTIDE010_ALTSTAT_CTRL;
|
|
|
+ ata_sff_std_ports(ioaddr);
|
|
|
+ }
|
|
|
+
|
|
|
+ dev_info(dev, "device ID %08x, irq %d, io base 0x%08x\n",
|
|
|
+ readl(ftide->base + FTIDE010_IDE_DEVICE_ID), irq, res->start);
|
|
|
+
|
|
|
+ ret = ata_host_activate(ftide->host, irq, ata_bmdma_interrupt,
|
|
|
+ 0, &pata_ftide010_sht);
|
|
|
+ if (ret)
|
|
|
+ goto err_dis_clk;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+err_dis_clk:
|
|
|
+ if (!IS_ERR(ftide->pclk))
|
|
|
+ clk_disable_unprepare(ftide->pclk);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int pata_ftide010_remove(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct ata_host *host = platform_get_drvdata(pdev);
|
|
|
+ struct ftide010 *ftide = host->private_data;
|
|
|
+
|
|
|
+ ata_host_detach(ftide->host);
|
|
|
+ if (!IS_ERR(ftide->pclk))
|
|
|
+ clk_disable_unprepare(ftide->pclk);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct of_device_id pata_ftide010_of_match[] = {
|
|
|
+ {
|
|
|
+ .compatible = "faraday,ftide010",
|
|
|
+ },
|
|
|
+ {},
|
|
|
+};
|
|
|
+
|
|
|
+static struct platform_driver pata_ftide010_driver = {
|
|
|
+ .driver = {
|
|
|
+ .name = DRV_NAME,
|
|
|
+ .of_match_table = of_match_ptr(pata_ftide010_of_match),
|
|
|
+ },
|
|
|
+ .probe = pata_ftide010_probe,
|
|
|
+ .remove = pata_ftide010_remove,
|
|
|
+};
|
|
|
+module_platform_driver(pata_ftide010_driver);
|
|
|
+
|
|
|
+MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
|
|
|
+MODULE_LICENSE("GPL");
|
|
|
+MODULE_ALIAS("platform:" DRV_NAME);
|
Linus Walleij