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@@ -209,6 +209,25 @@ static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
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return 0;
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}
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+static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
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+ unsigned int nvec, unsigned int pos)
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+{
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+ unsigned int i, res, bit, val;
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+
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+ i = 0;
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+ while (i < nvec) {
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+ irq_set_msi_desc_off(irq_base, i, NULL);
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+ clear_bit(pos + i, pp->msi_irq_in_use);
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+ /* Disable corresponding interrupt on MSI interrupt controller */
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+ res = ((pos + i) / 32) * 12;
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+ bit = (pos + i) % 32;
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+ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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+ val &= ~(1 << bit);
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+ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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+ ++i;
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+ }
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+}
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+
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static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
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{
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int res, bit, irq, pos0, pos1, i;
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@@ -242,11 +261,20 @@ static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
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if (!irq)
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goto no_valid_irq;
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+ /*
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+ * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
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+ * descs so there is no need to allocate descs here. We can therefore
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+ * assume that if irq_find_mapping above returns non-zero, then the
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+ * descs are also successfully allocated.
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+ */
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+
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i = 0;
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while (i < no_irqs) {
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+ if (irq_set_msi_desc_off(irq, i, desc) != 0) {
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+ clear_irq_range(pp, irq, i, pos0);
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+ goto no_valid_irq;
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+ }
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set_bit(pos0 + i, pp->msi_irq_in_use);
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- irq_alloc_descs((irq + i), (irq + i), 1, 0);
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- irq_set_msi_desc(irq + i, desc);
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/*Enable corresponding interrupt in MSI interrupt controller */
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res = ((pos0 + i) / 32) * 12;
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bit = (pos0 + i) % 32;
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@@ -266,7 +294,7 @@ no_valid_irq:
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static void clear_irq(unsigned int irq)
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{
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- int res, bit, val, pos;
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+ unsigned int pos, nvec;
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struct irq_desc *desc;
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struct msi_desc *msi;
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struct pcie_port *pp;
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@@ -281,18 +309,15 @@ static void clear_irq(unsigned int irq)
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return;
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}
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+ /* undo what was done in assign_irq */
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pos = data->hwirq;
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+ nvec = 1 << msi->msi_attrib.multiple;
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- irq_free_desc(irq);
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-
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- clear_bit(pos, pp->msi_irq_in_use);
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+ clear_irq_range(pp, irq, nvec, pos);
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- /* Disable corresponding interrupt on MSI interrupt controller */
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- res = (pos / 32) * 12;
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- bit = pos % 32;
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- dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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- val &= ~(1 << bit);
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- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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+ /* all irqs cleared; reset attributes */
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+ msi->irq = 0;
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+ msi->msi_attrib.multiple = 0;
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}
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static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
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