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@@ -1722,12 +1722,52 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
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}
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}
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+static bool broxton_phy_is_enabled(struct drm_i915_private *dev_priv,
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+ enum dpio_phy phy)
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+{
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+ if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
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+ return false;
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+
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+ if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
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+ (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
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+ DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
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+ phy);
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+
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+ return false;
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+ }
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+
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+ if (phy == DPIO_PHY1 &&
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+ !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
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+ DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
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+
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+ return false;
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+ }
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+
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+ if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
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+ DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
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+ phy);
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+
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+ return false;
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+ }
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+
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+ return true;
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+}
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+
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static void broxton_phy_init(struct drm_i915_private *dev_priv,
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enum dpio_phy phy)
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{
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enum port port;
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u32 ports, val;
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+ if (broxton_phy_is_enabled(dev_priv, phy)) {
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+ DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
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+ "won't reprogram it\n", phy);
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+
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+ return;
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+ }
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+
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+ DRM_DEBUG_DRIVER("DDI PHY %d not enabled, enabling it\n", phy);
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+
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val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
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val |= GT_DISPLAY_POWER_ON(phy);
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I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
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