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+* Broadcom STB NAND Controller
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+
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+The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
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+flash chips. It has a memory-mapped register interface for both control
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+registers and for its data input/output buffer. On some SoCs, this controller is
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+paired with a custom DMA engine (inventively named "Flash DMA") which supports
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+basic PROGRAM and READ functions, among other features.
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+
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+This controller was originally designed for STB SoCs (BCM7xxx) but is now
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+available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
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+iProc/Cygnus. Its history includes several similar (but not fully register
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+compatible) versions.
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+
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+Required properties:
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+- compatible : should contain "brcm,brcmnand" and an appropriate version
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+ compatibility string, like "brcm,brcmnand-v7.0"
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+ Possible values:
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+ brcm,brcmnand-v4.0
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+ brcm,brcmnand-v5.0
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+ brcm,brcmnand-v6.0
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+ brcm,brcmnand-v6.1
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+ brcm,brcmnand-v7.0
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+ brcm,brcmnand-v7.1
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+ brcm,brcmnand
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+- reg : the register start and length for NAND register region.
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+ (optional) Flash DMA register range (if present)
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+ (optional) NAND flash cache range (if at non-standard offset)
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+- reg-names : a list of the names corresponding to the previous register
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+ ranges. Should contain "nand" and (optionally)
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+ "flash-dma" and/or "nand-cache".
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+- interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available)
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+ FLASH_DMA_DONE
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+- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done"
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+- interrupt-parent : See standard interrupt bindings
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+- #address-cells : <1> - subnodes give the chip-select number
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+- #size-cells : <0>
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+
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+Optional properties:
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+- brcm,nand-has-wp : Some versions of this IP include a write-protect
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+ (WP) control bit. It is always available on >=
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+ v7.0. Use this property to describe the rare
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+ earlier versions of this core that include WP
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+
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+* NAND chip-select
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+
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+Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes
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+to represent enabled chip-selects which (may) contain NAND flash chips. Their
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+properties are as follows.
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+
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+Required properties:
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+- compatible : should contain "brcm,nandcs"
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+- reg : a single integer representing the chip-select
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+ number (e.g., 0, 1, 2, etc.)
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+- #address-cells : see partition.txt
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+- #size-cells : see partition.txt
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+- nand-ecc-strength : see nand.txt
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+- nand-ecc-step-size : must be 512 or 1024. See nand.txt
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+
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+Optional properties:
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+- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
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+ chip-select. See nand.txt
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+- brcm,nand-oob-sector-size : integer, to denote the spare area sector size
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+ expected for the ECC layout in use. This size, in
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+ addition to the strength and step-size,
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+ determines how the hardware BCH engine will lay
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+ out the parity bytes it stores on the flash.
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+ This property can be automatically determined by
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+ the flash geometry (particularly the NAND page
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+ and OOB size) in many cases, but when booting
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+ from NAND, the boot controller has only a limited
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+ number of available options for its default ECC
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+ layout.
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+
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+Each nandcs device node may optionally contain sub-nodes describing the flash
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+partition mapping. See partition.txt for more detail.
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+
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+Example:
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+
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+nand@f0442800 {
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+ compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
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+ reg = <0xF0442800 0x600>,
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+ <0xF0443000 0x100>;
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+ reg-names = "nand", "flash-dma";
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+ interrupt-parent = <&hif_intr2_intc>;
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+ interrupts = <24>, <4>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ nandcs@1 {
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+ compatible = "brcm,nandcs";
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+ reg = <1>; // Chip select 1
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+ nand-on-flash-bbt;
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+ nand-ecc-strength = <12>;
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+ nand-ecc-step-size = <512>;
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+
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+ // Partitions
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+ #address-cells = <1>; // <2>, for 64-bit offset
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+ #size-cells = <1>; // <2>, for 64-bit length
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+ flash0.rootfs@0 {
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+ reg = <0 0x10000000>;
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+ };
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+ flash0@0 {
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+ reg = <0 0>; // MTDPART_SIZ_FULL
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+ };
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+ flash0.kernel@10000000 {
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+ reg = <0x10000000 0x400000>;
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+ };
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+ };
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+};
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Brian Norris