Remove the majority of cache flushing calls from the individual platform files. This is now handled by the core code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
@@ -28,7 +28,6 @@ static inline void cpu_enter_lowpower_a9(void)
{
unsigned int v;
- flush_cache_all();
asm volatile(
" mcr p15, 0, %1, c7, c5, 0\n"
" mcr p15, 0, %1, c7, c10, 4\n"
@@ -15,8 +15,6 @@
*/
#include <linux/kernel.h>
-#include <asm/cacheflush.h>
-
#include "core.h"
#include "sysregs.h"
@@ -28,8 +26,6 @@ extern void secondary_startup(void);
void __ref highbank_cpu_die(unsigned int cpu)
highbank_set_cpu_jump(cpu, phys_to_virt(0));
highbank_set_core_pwr();
@@ -11,7 +11,6 @@
#include <linux/errno.h>
#include <asm/cp15.h>
#include "common.h"
@@ -20,7 +19,6 @@ static inline void cpu_enter_lowpower(void)
"mcr p15, 0, %1, c7, c5, 0\n"
@@ -10,16 +10,12 @@
#include <linux/smp.h>
#include <asm/smp_plat.h>
static inline void cpu_enter_lowpower(void)
- /* Just flush the cache. Changing the coherency is not yet
- * available on msm. */
}
static inline void cpu_leave_lowpower(void)
@@ -35,9 +35,6 @@ void __ref omap4_cpu_die(unsigned int cpu)
unsigned int boot_cpu = 0;
void __iomem *base = omap_get_wakeupgen_base();
- dsb();
/*
* we're ready for shutdown now, so do it
@@ -10,13 +10,10 @@
static inline void platform_do_lowpower(unsigned int cpu)
/* we put the platform to just WFI */
for (;;) {
__asm__ __volatile__("dsb\n\t" "wfi\n\t"
@@ -12,7 +12,6 @@
@@ -119,14 +119,6 @@ static int sh73a0_cpu_kill(unsigned int cpu)
static void sh73a0_cpu_die(unsigned int cpu)
- /*
- * The ARM MPcore does not issue a cache coherency request for the L1
- * cache when powering off single CPUs. We must take care of this and
- * further caches.
- */
/* Set power off mode. This takes the CPU out of the MP cluster */
scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF);
@@ -13,7 +13,6 @@
@@ -21,7 +20,6 @@ static inline void cpu_enter_lowpower(void)
" dsb\n"
#include <linux/clk/tegra.h>
#include "sleep.h"
#include <mach/setup.h>
@@ -24,8 +23,6 @@
void __ref ux500_cpu_die(unsigned int cpu)
/* directly enter low power state, skipping secure registers */