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@@ -2972,23 +2972,22 @@ i915_gem_find_active_request(struct intel_engine_cs *engine)
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struct i915_request *request, *active = NULL;
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unsigned long flags;
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- /* We are called by the error capture and reset at a random
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- * point in time. In particular, note that neither is crucially
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- * ordered with an interrupt. After a hang, the GPU is dead and we
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- * assume that no more writes can happen (we waited long enough for
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- * all writes that were in transaction to be flushed) - adding an
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+ /*
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+ * We are called by the error capture, reset and to dump engine
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+ * state at random points in time. In particular, note that neither is
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+ * crucially ordered with an interrupt. After a hang, the GPU is dead
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+ * and we assume that no more writes can happen (we waited long enough
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+ * for all writes that were in transaction to be flushed) - adding an
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* extra delay for a recent interrupt is pointless. Hence, we do
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* not need an engine->irq_seqno_barrier() before the seqno reads.
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+ * At all other times, we must assume the GPU is still running, but
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+ * we only care about the snapshot of this moment.
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*/
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spin_lock_irqsave(&engine->timeline.lock, flags);
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list_for_each_entry(request, &engine->timeline.requests, link) {
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if (__i915_request_completed(request, request->global_seqno))
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continue;
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- GEM_BUG_ON(request->engine != engine);
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- GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
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- &request->fence.flags));
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-
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active = request;
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break;
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}
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