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@@ -28,6 +28,12 @@ static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val)
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iowrite32(val, p->eth_csr_addr + offset);
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}
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+static void xgene_enet_wr_clkrst_csr(struct xgene_enet_pdata *p, u32 offset,
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+ u32 val)
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+{
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+ iowrite32(val, p->base_addr + offset);
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+}
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+
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static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *p,
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u32 offset, u32 val)
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{
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@@ -434,17 +440,38 @@ static void xgene_sgmac_tx_disable(struct xgene_enet_pdata *p)
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static int xgene_enet_reset(struct xgene_enet_pdata *p)
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{
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+ struct device *dev = &p->pdev->dev;
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+
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if (!xgene_ring_mgr_init(p))
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return -ENODEV;
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- if (!IS_ERR(p->clk)) {
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- clk_prepare_enable(p->clk);
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- clk_disable_unprepare(p->clk);
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- clk_prepare_enable(p->clk);
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+ if (p->enet_id == XGENE_ENET2)
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+ xgene_enet_wr_clkrst_csr(p, XGENET_CONFIG_REG_ADDR, SGMII_EN);
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+
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+ if (dev->of_node) {
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+ if (!IS_ERR(p->clk)) {
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+ clk_prepare_enable(p->clk);
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+ udelay(5);
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+ clk_disable_unprepare(p->clk);
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+ udelay(5);
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+ clk_prepare_enable(p->clk);
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+ udelay(5);
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+ }
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+ } else {
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+#ifdef CONFIG_ACPI
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+ if (acpi_has_method(ACPI_HANDLE(&p->pdev->dev), "_RST"))
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+ acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev),
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+ "_RST", NULL, NULL);
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+ else if (acpi_has_method(ACPI_HANDLE(&p->pdev->dev), "_INI"))
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+ acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev),
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+ "_INI", NULL, NULL);
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+#endif
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}
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- xgene_enet_ecc_init(p);
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- xgene_enet_config_ring_if_assoc(p);
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+ if (!p->port_id) {
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+ xgene_enet_ecc_init(p);
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+ xgene_enet_config_ring_if_assoc(p);
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+ }
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return 0;
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}
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@@ -492,6 +519,7 @@ static void xgene_enet_clear(struct xgene_enet_pdata *pdata,
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static void xgene_enet_shutdown(struct xgene_enet_pdata *p)
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{
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+ struct device *dev = &p->pdev->dev;
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struct xgene_enet_desc_ring *ring;
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u32 pb, val;
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int i;
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@@ -513,6 +541,11 @@ static void xgene_enet_shutdown(struct xgene_enet_pdata *p)
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pb |= BIT(val);
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}
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xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQRESET_ADDR, pb);
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+
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+ if (dev->of_node) {
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+ if (!IS_ERR(p->clk))
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+ clk_disable_unprepare(p->clk);
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+ }
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}
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static void xgene_enet_link_state(struct work_struct *work)
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