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@@ -30,8 +30,11 @@
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#define ANADIG_DIGPROG_IMX6SL 0x280
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#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
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+#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
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#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
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#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
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+/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
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+#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
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#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
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#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
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@@ -56,16 +59,43 @@ static void imx_anatop_enable_fet_odrive(bool enable)
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BM_ANADIG_REG_CORE_FET_ODRIVE);
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}
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+static inline void imx_anatop_enable_2p5_pulldown(bool enable)
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+{
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+ regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
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+ BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
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+}
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+
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+static inline void imx_anatop_disconnect_high_snvs(bool enable)
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+{
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+ regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
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+ BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
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+}
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+
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void imx_anatop_pre_suspend(void)
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{
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- imx_anatop_enable_weak2p5(true);
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+ if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
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+ imx_anatop_enable_2p5_pulldown(true);
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+ else
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+ imx_anatop_enable_weak2p5(true);
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+
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imx_anatop_enable_fet_odrive(true);
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+
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+ if (cpu_is_imx6sl())
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+ imx_anatop_disconnect_high_snvs(true);
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}
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void imx_anatop_post_resume(void)
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{
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+ if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
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+ imx_anatop_enable_2p5_pulldown(false);
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+ else
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+ imx_anatop_enable_weak2p5(false);
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+
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imx_anatop_enable_fet_odrive(false);
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- imx_anatop_enable_weak2p5(false);
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+
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+ if (cpu_is_imx6sl())
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+ imx_anatop_disconnect_high_snvs(false);
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+
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}
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static void imx_anatop_usb_chrg_detect_disable(void)
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