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@@ -259,7 +259,13 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
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fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
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fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
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} else {
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} else {
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- reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
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+ /* In order to prevent Tx hangs when the internal Tx
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+ * switch is enabled we must set the high water mark
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+ * to the Rx packet buffer size - 24KB. This allows
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+ * the Tx switch to function even under heavy Rx
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+ * workloads.
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+ */
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+ reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
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}
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}
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