|
@@ -13,16 +13,15 @@
|
|
|
|
|
|
#define __SWAB_64_THRU_32__
|
|
|
|
|
|
-#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \
|
|
|
- defined(_MIPS_ARCH_LOONGSON3A)
|
|
|
+#if !defined(__mips16) && \
|
|
|
+ ((defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \
|
|
|
+ defined(_MIPS_ARCH_LOONGSON3A))
|
|
|
|
|
|
-static inline __attribute__((nomips16)) __attribute_const__
|
|
|
- __u16 __arch_swab16(__u16 x)
|
|
|
+static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
|
|
|
{
|
|
|
__asm__(
|
|
|
" .set push \n"
|
|
|
" .set arch=mips32r2 \n"
|
|
|
- " .set nomips16 \n"
|
|
|
" wsbh %0, %1 \n"
|
|
|
" .set pop \n"
|
|
|
: "=r" (x)
|
|
@@ -32,13 +31,11 @@ static inline __attribute__((nomips16)) __attribute_const__
|
|
|
}
|
|
|
#define __arch_swab16 __arch_swab16
|
|
|
|
|
|
-static inline __attribute__((nomips16)) __attribute_const__
|
|
|
- __u32 __arch_swab32(__u32 x)
|
|
|
+static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
|
|
|
{
|
|
|
__asm__(
|
|
|
" .set push \n"
|
|
|
" .set arch=mips32r2 \n"
|
|
|
- " .set nomips16 \n"
|
|
|
" wsbh %0, %1 \n"
|
|
|
" rotr %0, %0, 16 \n"
|
|
|
" .set pop \n"
|
|
@@ -54,13 +51,11 @@ static inline __attribute__((nomips16)) __attribute_const__
|
|
|
* 64-bit kernel on r2 CPUs.
|
|
|
*/
|
|
|
#ifdef __mips64
|
|
|
-static inline __attribute__((nomips16)) __attribute_const__
|
|
|
- __u64 __arch_swab64(__u64 x)
|
|
|
+static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
|
|
|
{
|
|
|
__asm__(
|
|
|
" .set push \n"
|
|
|
" .set arch=mips64r2 \n"
|
|
|
- " .set nomips16 \n"
|
|
|
" dsbh %0, %1 \n"
|
|
|
" dshd %0, %0 \n"
|
|
|
" .set pop \n"
|
|
@@ -71,5 +66,5 @@ static inline __attribute__((nomips16)) __attribute_const__
|
|
|
}
|
|
|
#define __arch_swab64 __arch_swab64
|
|
|
#endif /* __mips64 */
|
|
|
-#endif /* MIPS R2 or newer or Loongson 3A */
|
|
|
+#endif /* (not __mips16) and (MIPS R2 or newer or Loongson 3A) */
|
|
|
#endif /* _ASM_SWAB_H */
|