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@@ -948,4 +948,53 @@ static inline int jedec_feature(struct nand_chip *chip)
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return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
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return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
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: 0;
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: 0;
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}
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}
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+
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+/**
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+ * struct nand_sdr_timings - SDR NAND chip timings
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+ *
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+ * This struct defines the timing requirements of a SDR NAND chip.
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+ * These informations can be found in every NAND datasheets and the timings
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+ * meaning are described in the ONFI specifications:
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+ * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
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+ * Parameters)
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+ *
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+ * All these timings are expressed in picoseconds.
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+ */
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+
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+struct nand_sdr_timings {
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+ u32 tALH_min;
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+ u32 tADL_min;
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+ u32 tALS_min;
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+ u32 tAR_min;
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+ u32 tCEA_max;
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+ u32 tCEH_min;
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+ u32 tCH_min;
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+ u32 tCHZ_max;
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+ u32 tCLH_min;
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+ u32 tCLR_min;
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+ u32 tCLS_min;
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+ u32 tCOH_min;
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+ u32 tCS_min;
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+ u32 tDH_min;
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+ u32 tDS_min;
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+ u32 tFEAT_max;
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+ u32 tIR_min;
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+ u32 tITC_max;
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+ u32 tRC_min;
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+ u32 tREA_max;
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+ u32 tREH_min;
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+ u32 tRHOH_min;
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+ u32 tRHW_min;
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+ u32 tRHZ_max;
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+ u32 tRLOH_min;
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+ u32 tRP_min;
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+ u32 tRR_min;
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+ u64 tRST_max;
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+ u32 tWB_max;
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+ u32 tWC_min;
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+ u32 tWH_min;
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+ u32 tWHR_min;
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+ u32 tWP_min;
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+ u32 tWW_min;
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+};
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#endif /* __LINUX_MTD_NAND_H */
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#endif /* __LINUX_MTD_NAND_H */
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