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@@ -42,6 +42,28 @@ struct amdgpu_cgs_device {
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struct amdgpu_device *adev = \
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((struct amdgpu_cgs_device *)cgs_device)->adev
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+static void *amdgpu_cgs_register_pp_handle(struct cgs_device *cgs_device,
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+ int (*call_back_func)(struct amd_pp_init *, void **))
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+{
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+ CGS_FUNC_ADEV;
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+ struct amd_pp_init pp_init;
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+ struct amd_powerplay *amd_pp;
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+
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+ if (call_back_func == NULL)
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+ return NULL;
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+
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+ amd_pp = &(adev->powerplay);
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+ pp_init.chip_family = adev->family;
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+ pp_init.chip_id = adev->asic_type;
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+ pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
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+ pp_init.feature_mask = amdgpu_pp_feature_mask;
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+ pp_init.device = cgs_device;
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+ if (call_back_func(&pp_init, &(amd_pp->pp_handle)))
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+ return NULL;
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+
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+ return adev->powerplay.pp_handle;
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+}
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+
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static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
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enum cgs_gpu_mem_type type,
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uint64_t size, uint64_t align,
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@@ -1179,6 +1201,7 @@ static const struct cgs_ops amdgpu_cgs_ops = {
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.is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
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.enter_safe_mode = amdgpu_cgs_enter_safe_mode,
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.lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
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+ .register_pp_handle = amdgpu_cgs_register_pp_handle,
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};
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static const struct cgs_os_ops amdgpu_cgs_os_ops = {
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